A semiconductor device includes a substrate. The semiconductor device further includes a conductive structure in the substrate. The semiconductor device further includes an etch stop layer over the substrate. The semiconductor device further includes an interlayer dielectric (ILD) over the etch stop layer. The semiconductor device further includes a dual damascene conductive element in the ILD, wherein the dual damascene conductive element extends through the etch stop layer to electrically connect to the conductive structure, and the dual damascene conductive element has a line end roughness (LER) ranging from 3.3 nanometers (nm) to 5.3 nm.

A semiconductor processing system includes a layout database that stores a plurality of layouts indicating features to be formed in a wafer. The semiconductor processing system includes a layout analyzer that analyzes the layouts and determines, for each layout, whether a non-perpendicular particle bombardment process should be utilized in conjunction with a photolithography process for forming the features of the layout in a wafer.

A method of patterning a substrate includes exposing a photoresist layer on the substrate with a pattern of actinic radiation to form a chemically reactive surface pattern, and coating, at the track system, a spin-on-material to convert the chemically reactive surface pattern to a photoresist surface mask pattern. The method further includes etching the photoresist layer using the photoresist surface mask pattern as a first etch mask to form a photoresist mask pattern, and etching a layer to be etched with the photoresist mask pattern as a second etch mask.

A semiconductor device including a cap layer and a method for forming the same are disclosed. In an embodiment, a method includes epitaxially growing a first semiconductor layer over an N-well; etching the first semiconductor layer to form a first recess; epitaxially growing a second semiconductor layer filling the first recess; etching the second semiconductor layer, the first semiconductor layer, and the N-well to form a first fin; forming a shallow trench isolation region adjacent the first fin; and forming a cap layer over the first fin, the cap layer contacting the second semiconductor layer, forming the cap layer including performing a pre-clean process to remove a native oxide from exposed surfaces of the second semiconductor layer; performing a sublimation process to produce a first precursor; and performing a deposition process wherein material from the first precursor is deposited on the second semiconductor layer to form the cap layer.

Technologies are described for methods and systems effective for etching nanostructures in a substrate. The methods may comprise depositing a patterned block copolymer on the substrate. The methods may comprise applying a precursor to the patterned block copolymer to generate an infiltrated block copolymer. The precursor may infiltrate into the first polymer block domain and generate a material. The methods may comprise applying a removal agent effective to remove the polymer block domains to the infiltrated block copolymer to generate a pattern of the material. The methods may comprise etching the substrate. The pattern of the material may mask the substrate to pattern the etching. The etching may be performed under conditions to produce nanostructures in the substrate. The methods may comprise removing the pattern of the material and coating the nanostructures and the surface of the substrate with a hydrophobic coating.

The present invention relates to a substrate treating method for treating a substrate. The substrate treating method includes a development step, a treatment liquid supply step, a solidified film forming step, and a sublimation step. In the development step, a developer is supplied to a substrate. In the treatment liquid supply step, a treatment liquid is supplied to the substrate. The treatment liquid contains a sublimable substance and a solvent. In the solidified film forming step, the solvent of the treatment liquid evaporates from the treatment liquid on the substrate. In the solidified film forming step, the solidified film is formed on the substrate. The solidified film contains the sublimable substance. In the sublimation step, the solidified film sublimates.

A method includes depositing a dielectric layer over a semiconductor substrate; forming a first photoresist layer over the dielectric layer; patterning the first photoresist layer to form through holes, such that a first portion of the first photoresist layer between a first one and a second one of the through holes has a less height than a second portion of the first photoresist layer between the first one and a third one of the through holes; forming a spacer on the first portion of the first photoresist layer; performing an etching process on the dielectric layer to form via holes while the spacer remains covering the first portion of the first photoresist layer; forming a plurality of metal vias in the via holes.

Semiconductor devices and corresponding methods of manufacture are disclosed. The method may include forming a first hardmask layer over a substrate. The method may include forming a second hardmask layer over the first hardmask layer. The method may include transferring a pattern from the second hardmask layer to the first hardmask layer, wherein the pattern in the first hardmask layer comprises a plurality of protruding structures, and each of the plurality of protruding structures has respective portions of its two sidewalls extending toward each other. The method may include depositing a modification layer extending along at least the respective portions of the sidewalls of each of the protruding structures. The method may include etching the substrate with the protruding structures and the modification layer both serving as a mask.

An element includes a substrate and a surface layer on the substrate. The surface layer includes at least one first region comprising an optically transparent and electrically insulative first material and at least one second region at least partially embedded in the at least one first region. The at least one second region comprises an optically transparent and electrically conductive second material.

A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.