Power delivery is enabled for wafer-scale integration. A wafer-scale silicon interposer (WSSI) is accessed. A front side of the WSSI is bonded to a plurality of functional chips. The WSSI includes a plurality of through-silicon vias (TSVs). The WSSI is associated with a first coefficient of thermal expansion (CTE). An anisotropic conductive film (ACF) is coupled to a back side of the WSSI. A plurality of modular power substrates (MPSs) is further coupled, based on the plurality of TSVs, to one or more functional chips. The MPSs are connected mechanically to a unified control board (UCB). The UCB includes a plurality of DC-to-DC power converters. The UCB is associated with a second coefficient of thermal expansion. The UCB sends DC power to the plurality of functional chips. The sending includes one or more voltage conversions and is based on the plurality of MPSs.

A packaging device including bumps and a method of manufacturing the packaging device are presented. In the method of manufacturing a packaging device, a dielectric layer that covers a packaging base is formed and a lower layer is formed over a packaging base including first and second connecting pads. A plurality of dummy bumps that overlaps with the dielectric layer is formed. A sealing pattern that covers the dummy bumps, filling areas between the dummy bumps, is formed. A lower layer pattern in which the plurality of dummy bumps have been disposed is formed by removing portions of the lower layer that are exposed and do not overlap with the sealing pattern.