A 3D SoC device includes an intermediate redistribution layer, a lower semiconductor module, and an upper semiconductor module. The intermediate redistribution layer electrically connects the lower semiconductor module to the upper semiconductor module and further connects to an external power source. The lower semiconductor module includes a lower dielectric layer, a lower insulating layer, a plurality of lower conductive posts, a lower chip unit, and a plurality of solder balls. The lower chip unit is composed of a plurality of SoC processing chips located in the lower dielectric layer. The upper semiconductor module includes an upper dielectric layer, and a plurality of upper layer chips.

An electronic device according to the present disclosure includes a semiconductor substrate, a chip, and a bump. The chip has a thermal expansion coefficient different from that of the semiconductor substrate. The bump connects the connection pads provided on the opposing principal surfaces of the semiconductor substrate and the chip. The bump has a porous metal layer and a metal film. The metal film is provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on the side surfaces of the porous metal layer.

A wafer-level chip structure, a multiple-chip stacked and interconnected structure and a fabricating method thereof, wherein the wafer-level chip structure includes: a through-silicon via, which penetrates a wafer; a first surface including an active region, a multi-layered redistribution layer and a bump; and a second surface including an insulation dielectric layer, and a frustum transition structure connected with the through-silicon via. In an embodiment of the present application, a frustum type impedance transition structure is introduced into a position between a TSV exposed area on a backside of a wafer and a UBM so as to implement an impedance matching between TSV and UBM, thereby alleviating the problem of signal distortion that is caused by an abrupt change of impedance.

A method for manufacturing a semiconductor device includes providing a semiconductor element having electrode terminals; forming a resist on the semiconductor element, the resist having a first surface facing the electrode terminals and a second surface opposite to the first surface; forming an opening in the resist, which covers the electrode terminals by inserting protrusions of a mold into the resist above the electrode terminals; curing the resist by applying energy to the resist; and widening the opening in a radial direction of the opening. The resist is cured in a state where the second surface of the resist faces an inner surface of the mold with a gap between the second surface of the resist and the inner surface of the mold.

A semiconductor device and a method of forming the same are provided. The semiconductor device includes an integrated circuit die, a dielectric layer, an under-bump metallurgy layer, an interconnection die, and a solder material. The integrated circuit die includes a first die connector. The dielectric layer is located on the integrated circuit die. The under-bump metallurgy layer has a line portion on the dielectric layer and a via portion extending through the dielectric layer to contact the first die connector. The interconnection die includes a second die connector. The solder material is located between the line portion of the under-bump metallurgy layer and the second die connector. The under-bump metallurgy layer includes a first copper layer having a uniform grain orientation, wherein the top surface of the first copper layer is in direct contact with the solder material.

A method of making a semiconductor assembly may include mounting a plurality of components to a patterned element on an intermediate carrier, and disposing an encapsulant over the intermediate carrier, where the encapsulant may be disposed around four side surfaces of each of the plurality of components and one or more of the plurality of components may comprise conductive studs disposed over a front surface of the components. The method may further include removing a portion of the encapsulant to form a planar surface above the front surface, wherein the planar surface comprises ends of the conductive studs and a planar surface of the encapsulant. The method may further comprise removing the intermediate carrier through a grinding process, and terminating the grinding process when at least a portion of the patterned element is exposed.

A semiconductor package and a method for manufacturing a semiconductor package includes a base substrate including a first surface and a second surface, a first contact pad disposed on the first surface of the base substrate, a first solder resist layer disposed on the first surface of the base substrate, a second solder resist layer covering a portion of an upper surface of the first solder resist layer, and a first connector disposed in the first opening area and the second opening area. The first solder resist layer covers a side surface and a portion of an upper surface of the first contact pad, and defines a first opening area on the first contact pad. The first connector is in contact with the first contact pad. A first width of the first opening area is smaller than a second width of the second opening area.

In examples, a semiconductor package includes a semiconductor die having a device side in which circuitry is formed; multiple copper posts coupled to the device side of the semiconductor die; a substrate coupled to the multiple copper posts by solder joints, the substrate comprising: cylindrical copper pillars extending from the solder joints on a top surface of the substrate to a bottom surface of the substrate, the copper pillars having circular or ovoid bottom surfaces exposed to the bottom surface of the substrate; and a build-up film between and physically contacting the copper pillars. The package also includes a mold compound physically contacting the semiconductor die, the multiple copper posts, and the top surface of the substrate.

Methods and devices for implementing vias as third-dimension connections in double-sided laminate packages for RF front-end circuits are disclosed. The described methods and devices are based on implementing components of an electronic module in two different integrated circuits and dispose the two integrated circuits on the opposite side of an isolating laminate. The components within one integrated circuit can be coupled to the components on the other integrated circuit by creating vias inside the laminate.

Provided are a chip packaging method and a chip packaging structure. The method includes: arranging a spacer on at least one of a first surface of a package substrate and a second surface of a chip; arranging a first adhesive on at least one of the first surface, the second surface, or the spacer; bringing together the package substrate and the chip, to sandwich the spacer between the first surface and the second surface, and adhere the first surface to the second surface by the first adhesive; and curing the first adhesive. With the chip packaging structure generated based on the above-mentioned method, a shear displacement of the first adhesive can be increased under a given load to reduce an attachment area of the chip, ensuring a height of the first adhesive.