Technologies for chip-to-chip (C2C) yield and performance optimization in a die stacking platform are described. One stacked die platform includes a substrate, a first die and a second die stacked together, and first and C2C interfaces on the first and second dies, respectively. The stacked die platform also includes switching circuitry and a link monitoring unit. The switching circuitry is configured to selectively connect either the first C2C interface or the second C2C interface to the bump connections, where only one of the first C2C interface and the second C2C interface is active at a time. The link monitoring unit is configured to monitor link status and control operation of the switching circuitry to provide redundancy for C2C communication failures.

A wafer-on-wafer bonded memory and logic device can enable high bandwidth transmission of data directly between a memory die and a logic die. A memory device formed on a memory die can include many global input/output lines and many arrays of memory cells. Each array of memory cells can include respective local input/output (LIO) lines coupled to a global input/output line. A logic device can be formed on a logic die. A bond, formed between the memory die and the logic die via a wafer-on-wafer bonding process, can couple the many global input/output lines to the logic device.

An electronic package is provided, in which a cover layer is embedded in a circuit structure to form a groove, and an electronic element is disposed on the cover layer in the groove. A cladding layer encapsulates the electronic element, and an external connection structure is disposed on the circuit structure and the cladding layer. Therefore, the electronic element is embedded in the groove, such that a thickness of the electronic package can be greatly reduced to meet the requirement of thinning.

A semiconductor package is provided. The semiconductor package includes a semiconductor device bonded to a base through a first conductive structure. The semiconductor device includes a carrier substrate including a conductive trace. A portion of the conductive trace is elongated. The semiconductor device also includes a second conductive structure above the carrier substrate. A portion of the second conductive structure is in contact with the portion of the conductive trace. The semiconductor device further includes a semiconductor body mounted above the conductive trace. The semiconductor body is connected to the second conductive structure.

An electronic package is provided, in which a circuit structure is stacked on a carrier structure having a routing layer via support structures, where electronic elements are disposed on upper and lower sides of the circuit structure and the carrier structure, and the electronic elements and the support structures are encapsulated by a cladding layer, such that the electronic package can effectively increase the packaging density to meet the requirements of multi-functional end products.

An electrically non-conducting film (109) comprising an oligomer comprising an arylene or heteroarylene repeating unit is disposed between a chip (105), e.g. a flip-chip, and a functional layer (101), e.g. a printed circuit board, electrically connected to the chip by electrically conducting interconnects (107). The oligomer may be crosslinked.

A semiconductor package structure includes a first package component, a second package component disposed over the first package component, a plurality of connectors between the first package component and the second package component, an underfill between the first package component and the second package component and surrounding the plurality of connectors, and a plurality of heat sink fibers in the underfill. A thermal conductivity of the plurality of heat sink fibers is greater than a thermal conductivity of the underfill.

Embodiments herein relate to systems, apparatuses, or processes for creating packages that include one or more memory modules with electrically conductive strips on the side of the memory module to route power or provide a ground to multiple BGA contacts on a side of the memory module coupled with a substrate. Providing power and/or ground in this manner enables fewer layers to be used in a substrate that are no longer needed to be routed in the power plane on the substrate, thus reducing a Z-height of the package. Other embodiments may be described and/or claimed.

A memory device including a module substrate having a first side surface and a second side surface perpendicular to the first side surface, a semiconductor package disposed on at least one of an upper surface and a lower surface of the module substrate, a passive device disposed on at least one of the upper surface and the lower surface of the module substrate, wherein the passive device is electrically connected to the semiconductor package, and a protective layer disposed on and covering the passive device. The module substrate includes a connector adjacent to the first side surface, the passive device includes a first passive device disposed between the connector and the semiconductor package, and the protective layer includes a first protective layer covering at least a portion of the first passive device.

A semiconductor structure includes a semiconductor die, a redistribution circuit structure, and a terminal. The redistribution circuit structure is disposed on and electrically coupled to the semiconductor die. The terminal is disposed on and electrically coupled to the redistribution circuit structure, where the redistribution circuit structure is disposed between the semiconductor die and the terminal, and the terminal includes an under-bump metallization (UBM) and a capping layer. The UBM is disposed on and electrically coupled to the redistribution circuit structure, where the UBM includes a recess. The capping layer is disposed on and electrically coupled to the UBM, where the UBM is between the capping layer and the redistribution circuit structure, and the capping layer fills the recess of the UBM.