A semiconductor device and a method of making the same are provided. A first die and a second die are placed over a carrier substrate. A first molding material is formed adjacent to the first die and the second die. A first redistribution layer is formed overlying the first molding material. A through via is formed over the first redistribution layer. A package component is on the first redistribution layer next to the copper pillar. The package component includes a second redistribution layer. The package component is positioned so that it overlies both the first die and the second die in part. A second molding material is formed adjacent to the package component and the first copper pillar. A third redistribution layer is formed overlying the second molding material. The second redistribution layer is placed on a substrate and bonded to the substrate.

A method includes dispensing sacrificial region over a carrier, and forming a metal post over the carrier. The metal post overlaps at least a portion of the sacrificial region. The method further includes encapsulating the metal post and the sacrificial region in an encapsulating material, demounting the metal post, the sacrificial region, and the encapsulating material from the carrier, and removing at least a portion of the sacrificial region to form a recess extending from a surface level of the encapsulating material into the encapsulating material.

The present disclosure relates to at least one embodiment of an electronic chip that includes an integrated circuit formed in and on a semiconductor substrate. The flanks of the substrate being coated with a second protective resin. The electronic chip further includes at least one metal contact arranged on a first face of the semiconductor substrate and extending laterally beyond the flanks of the second protective resin. Said at least one metal contact may have a flat connection face extending continuously in part under the semiconductor substrate and extending laterally beyond the flanks of the second protective resin.

A semiconductor device includes: a first semiconductor element; a first terminal positioned on a first side in a first direction relative to the first semiconductor element; a protective layer of an insulator partially covering the first semiconductor element; and a first conductive member electrically connected to the first semiconductor element and the first terminal. The protective layer is spaced apart from the first terminal. The first conductive member is positioned between the first semiconductor element and the first terminal in the first direction. The first conductive member includes a first portion overlapping with the protective layer as viewed in a direction perpendicular to the first direction, and a second portion connected to the first portion and positioned on a side opposite the first semiconductor element with respect to the first portion. The second portion protrudes from the protective layer as viewed in a direction perpendicular to the first direction.

A semiconductor package includes a first rewiring layer; a lower semiconductor chip on the first rewiring layer; an upper semiconductor chip on the lower semiconductor chip; a heat dissipation structure on the upper semiconductor chip; a molding layer on the first rewiring layer so as to contact side surfaces of the lower semiconductor chip, the upper semiconductor chip, and the heat dissipation structure; a second rewiring layer on the heat dissipation structure; and one or more connection structures on the first rewiring layer and positioned adjacent to the side surfaces of the lower semiconductor chip and the upper semiconductor chip and configured to extend through the molding layer and connect the first rewiring layer to the second rewiring layer, wherein the upper semiconductor chip and the heat dissipation structure contact each other.

A device package including an interposer. The interposer comprising: a semiconductor substrate; first through vias extending through the semiconductor substrate; an interconnect structure comprising: a first metallization pattern in an inorganic insulating material; and a passivation film over the first metallization pattern; and a first redistribution structure over the passivation film. The first redistribution structure comprising a second metallization pattern in an organic insulating material. The device package further including an integrated circuit die over and attached to the interposer; and a first encapsulant around the integrated circuit die.

A sensor package structure and a manufacturing method thereof are provided. The sensor package structure includes a substrate, a fixing adhesive layer disposed on the substrate, a sensor chip adhered to the fixing adhesive layer, an annular adhering layer disposed on the sensor chip, a light-permeable sheet adhered to the annular adhering layer, and a plurality of metal wires that are electrically coupled to the substrate and the sensor chip. The size of the light-permeable sheet is smaller than that of the sensor chip.

A package structure includes at least one integrated circuit component, an insulating encapsulation, and a redistribution structure. The at least one integrated circuit component includes a semiconductor substrate, an interconnection structure disposed on the semiconductor substrate, and signal terminals and power terminals located on and electrically connecting to the interconnection structure. The interconnection structure is located between the semiconductor substrate and the signal terminals and between the semiconductor substrate and the power terminals, and where a size of the signal terminals is less than a size of the power terminals. The insulating encapsulation encapsulates the at least one integrated circuit component. The redistribution structure is located on the insulating encapsulation and electrically connected to the at least one integrated circuit component.

In examples, a semiconductor package comprises a semiconductor die having a first surface on which circuitry is formed and a second surface opposite the first surface. The semiconductor package includes a mold compound, the second surface facing the mold compound. The mold compound covers the semiconductor die; a set of conductive vias exposed to a top surface of the mold compound and coupled to a metal layer in the package; a set of first conductive members vertically aligned with the semiconductor die and exposed to the top surface of the mold compound; and a set of second conductive members coupling at least some of the set of conductive vias to at least some of the set of first conductive members. The set of second conductive members is exposed to the top surface of the mold compound.

A semiconductor package includes a redistribution layer, a first substrate disposed on the redistribution layer and having a first cavity, a first semiconductor chip in the first cavity and having a first connection pad, a first encapsulant covering the first semiconductor chip and filling the first cavity, a second substrate disposed on the first substrate and having a second cavity, a second semiconductor chip in the second cavity and having a second connection pad, a second encapsulant covering the second semiconductor chip and filling the second cavity, a first connection via penetrating through the first encapsulant, directly connected to the first connection pad, and connecting the first connection pad to the redistribution layer, and a second connection via penetrating through the first substrate and the first and second encapsulants, directly connected to the second connection pad, and connecting the second connection pad to the redistribution layer.