A memory device includes a first case, a second case coupled to the first case, a mid plate placed in an inner space between the first and second cases, a first memory module between the first case and the mid plate, including a first module substrate and at least one first electronic chip on the first module substrate, and a second memory module between the second case and the mid plate, including a second module substrate and at least one second electronic chip on the second module substrate, wherein the mid plate includes a base unit, a first rib structure extending from the base unit to electrically connect the mid plate to the first module substrate, and a second rib structure spaced apart from the first rib structure to electrically connect the mid plate to the first module substrate.

A stacked substrate structure and a manufacturing method thereof are provided. The stacked substrate structure includes a first structure and a second structure. The first structure has a first bonding surface and includes a first circuit structure. The first circuit structure includes a plurality of first conductive layers and a first expansion modulation layer. The plurality of first conductive layers are stacked in a vertical direction. The first expansion modulation layer is disposed between the adjacent first conductive layers. A coefficient of thermal expansion of the first expansion modulation layer is greater than a coefficient of thermal expansion of the plurality of first conductive layers. The second structure has a second bonding surface, and the second bonding surface of the second structure faces the first bonding surface of the first structure.

Implementations of a semiconductor device may include a first largest planar surface, a second largest planar surface and a thickness between the first largest planar surface and the second largest planar surface; and one of a permanent die support structure, a temporary die support structure, or any combination thereof coupled to one of the first largest planar surface, the second largest planar surface, the thickness, or any combination thereof. The first largest planar surface, the second largest planar surface, and the thickness may be formed by at least two semiconductor die. The warpage of one of the first largest planar surface or the second largest planar surface may be less than 200 microns.

An integrated circuit package structure includes a first substrate and a second substrate. The first substrate includes a sensor and a metal routing connecting to the sensor. The second substrate is bonded to the first substrate and includes a circuit layer and a plurality of conductive connectors connecting to the circuit layer. At least one of the first substrate and the second substrate further includes a stacked metal structure configured to provide electrostatic discharge protection.