A sensing device includes a sensing chip, which has an active face with a sensing region and a metal pad region having at least a metal pad thereon; a dielectric layer, which covers a periphery, back surface and a part of the active surface of the sensing chip, and the first face of the dielectric layer has an elevation higher than the active face of the sensing chip and exposes the sensing region of the sensing chip; a first conductive wire layer and a second conductive wire layer, which are disposed on the first and second faces of the dielectric layer respectively; a conductive pillar, which is disposed within the dielectric layer and connected to the first and second conductive wire layers; and a front-face fan-out circuit, which is connected to the first conductive wire layer and the metal pad of the sensing chip.

A substrate includes a base plate made of an insulating material, a first electrically conductive layer disposed on a first side of the base plate, and a second electrically conductive layer disposed on a second side of the base plate. The first electrically conductive layer has a stepped surface, the stepped surface including a plurality of steps at different heights above the base plate.

A power electronics module, having a PCB having power semiconductors arranged on connecting regions of an uppermost layer of said PCB, wherein the PCB has a preset dimension to arrange a preset maximum number of power semiconductors thereon. A lead frame arranged above the power semiconductors provides three-dimensional power and control routing, and includes a drain-source connection to connect to a drain-source contact of the PCB, and a load-source connection opposite the drain-source connection via the power semiconductors that is formed from a plurality of subregions, each of which can be brought into electrical contact with the power semiconductors, and a gate- and kelvin-source terminal, which are arranged above the load-source connection and have been brought into electrical contact with the power semiconductors. At least one dummy chip consisting of an electrically nonconductive material is arranged on each of the connecting regions that are not populated by power semiconductors.

Aspects of the present disclosure include systems, structures, circuits, and methods providing integrated circuit (IC) packages or modules having diagonalized leads. First and second semiconductor dies are disposed on a substrate. First and second coils are configured on the substrate for a transformer. The transformer may include a core. The leads or pins may be aligned along a diagonal of the package body, providing increased creepage. The IC packages and modules may include various types of circuits; in some examples, IC packages or modules may include a galvanically isolated gate driver or other high voltage circuit.