A semiconductor package carrier structure is provided and includes a substrate body, a dielectric material, and a patterned circuit layer. The substrate body has a plurality of openings, a plurality of conductive pillars, and at least one die placement portion. The dielectric material is disposed in the plurality of openings. The patterned circuit layer is disposed on a surface of the substrate body. Side surfaces of the plurality of conductive pillars and the die placement portion are all in a concave arc shape. The patterned circuit layer includes a die placement pad corresponding to the die placement portion and a plurality of bonding pads corresponding to the plurality of conductive pillars. A method of manufacturing the semiconductor package carrier structure is further provided.

A semiconductor package includes a substrate including a die pad, first and second discrete transistor dies mounted on the die pad, an encapsulant body that encapsulates the first and second discrete transistor dies, and a plurality of leads that are exposed from the encapsulant body, wherein the first and second discrete transistor dies are connected in parallel with one another by electrical interconnections that electrically connect common terminals of the first and second discrete transistor dies to one of the leads, and wherein at least one of the electrical interconnections has a balanced configuration that provides substantially identical electrical impedance as between the common terminals of the first and second discrete transistor dies and the lead to which they are connected.

An electronic device includes a leadframe where the leadframe includes a first set of leads, a second set of leads, and conductive pads. A heat sink is attached to the conductive pads. The heat sink includes a pair of heat sink pads separated by a gap, and a die attach pad. The die attach pad has a semi-circular shape and is connected to an end of each of the pair of heat sink pads to form a U-shape. The die attach pad further includes an airgap prevention feature. A die is attached to the heat sink and wire bonds connect the die to the leadframe. A mold compound encapsulates the heat sink, the die, and the wire bonds.

A method includes removing an oxide layer from select areas of a surface of a metal structure of a lead frame to create openings that extend through the oxide layer to expose portions of the surface of the metal structure. The method further includes attaching a semiconductor die to the lead frame, performing an electrical connection process that electrically couples an exposed portion of the surface of the metal structure to a conductive feature of the semiconductor die, enclosing the semiconductor die in a package structure, and separating the electronic device from the lead frame. In one example, the openings are created by a laser ablation process. In another example, the openings are created by a chemical etch process using a mask. In another example, the openings are created by a plasma process.

An electronic device includes: an insulating substrate including an obverse surface facing a thickness direction; a wiring portion formed on the substrate obverse surface and made of a conductive material; a lead frame arranged on the substrate obverse surface; a first and a second semiconductor elements electrically connected to the lead frame; and a first control unit electrically connected to the wiring portion to operate the first semiconductor element as a first upper arm and operate the second semiconductor element as a first lower arm. The lead frame includes a first pad portion to which the first semiconductor element is joined and a second pad portion to which the second semiconductor element is joined. The first and second pad portions are spaced apart from the wiring portion and arranged in a first direction with a first separation region sandwiched therebetween, where the first direction is orthogonal to the thickness direction. The first control unit is spaced apart from the lead frame as viewed in the thickness direction, while overlapping with the first separation region as viewed in a second direction orthogonal to the thickness direction and the first direction.

A bonding region is specified by having a horizontal line partially constituting crosshairs displayed on a monitor of a wire bonding apparatus superimposed on a first line segment of a first marker, and having a vertical line partially constituting the crosshairs superimposed on a first line segment of a second marker.

A resin enclosure includes: an inner wall portion from a wall surface defining the space to a side surface of the lead terminal close to the space; and a covering portion that covers at least a part of a top surface of a first portion of the lead terminal.

A semiconductor device is provided, which is configured to improve the adhesion between the resin part and the leads without interfering with proper operation of the semiconductor device. The semiconductor device includes a semiconductor element 1, a first lead 2 including a first pad portion 21, a second lead 3 including a second pad portion 31, a conductor member 61, and a resin part 8. The first pad portion 21 has a first-pad obverse surface 21a including a first smooth region 211 to which an element reverse surface 1b is bonded, and a first rough region 212 spaced apart from the semiconductor element 1 as viewed in z direction and has a higher roughness than the first smooth region 211. The second pad portion 31 has a second-pad obverse surface 31a including a second smooth region 311 to which a second bonding portion 612 is bonded, and a second rough region 312 spaced apart from the second bonding portion 612 as viewed in z direction and has a higher roughness than the second smooth region 311.

A package includes a first carrier including a component mounting area, a second carrier including at least one lead section, at least one electronic component mounted on the component mounting area, and an encapsulant encapsulating at least part of the at least one electronic component, encapsulating at least part of the first carrier including encapsulating the entire sidewalls of the first carrier, and encapsulating part of the second carrier, wherein the first carrier is assembled with the second carrier so that the at least one electronic component and/or the first carrier is electrically connected with the at least one lead section, and wherein the first carrier has a first thickness and the second carrier has a second thickness being smaller than the first thickness.

According to an embodiment, a semiconductor device having a first surface facing a first side and a second surface facing a second side opposite to the first side is provided. The semiconductor device of the embodiment includes a semiconductor device body, a lead frame to which the semiconductor device body is electrically connected, a conductive bump portion electrically connected to a semiconductor device body or the lead frame, and a resin portion configured to cover and hold at least a part of the semiconductor device body and at least a part of the lead frame. At least a part of the conductive bump portion is exposed outside the resin portion.