The present disclosure proposes a semiconductor device, as well as a method for manufacturing such a semiconductor device, and related to a method of generating a dual exposed drain with common gate and source clip-bonded package for reverse battery protection. The semiconductor device includes a first lead frame with an external first lead frame terminal and a first die paddle, a second lead frame with an external second lead frame terminal and a second die paddle, a common clip with an external source clip terminal, a two source contacts, a common gate clip with an external common clip gate terminal, a clip contact and a gate clip contact, a first semiconductor die with a first die gate terminal, a first die source terminal, and a first die drain terminal, a second semiconductor die with a second die gate terminal, a second die source terminal, and a second die drain terminal.

A semiconductor package includes: a first transistor chip having opposite first and second sides, the first side including source chip pad(s) (S1) and drain chip pad(s) (D1); a second transistor chip having opposite first and second sides, the first side including source chip pad(s) (S2) and drain chip pad(s) (D2); and a chip carrier having opposite first and second main sides. The first main side of the chip carrier faces the first side of the first transistor chip and is attached to S1 and D1. The second main side of the chip carrier faces the first side of the second transistor chip and is attached to S2 and D2. The chip carrier is configured to electrically connect the transistor chips in a D1-S1-D2-S2, S1-D1-D2-S2 or D1-S1-S2-D2 configuration, and configured to be attached to an application board in an inclined orientation relative to the application board.

A semiconductor package and method are disclosed. In one example, the semiconductor package includes a package body. A first diepad is at least partially uncovered by the package body at the first main surface. A second diepad is at least partially uncovered by the package body at the first main surface. A first semiconductor chip is arranged on the first diepad. A second semiconductor chip is arranged on the second diepad. The semiconductor package further includes at least one lead protruding out of the package body at the side surface. A first groove and a second groove are formed in the first main surface. The method includes a method of making the semiconductor package.

A module includes an assembly of a semiconductor device die coupled to a lead frame. A board is disposed below the lead frame. The board includes a plated-through hole (PTH) aligned with an opening in the lead frame above the board. The module further includes a mold body encapsulating at least a portion of the assembly. The mold body includes a through-mold via (TMV) aligned with the opening in the lead frame and with the PTH. The PTH is physically accessible from outside the mold body through the TMV and the opening in the lead frame.

A chip package structure includes a die pad, input/output pads, a chip, first bonding wires, a molding compound, a solder resist layer, first solder balls and second solder balls. The input/output pads are configured around the die pad. The chip is configured on the die pad. The first bonding wires are electrically connected to the chip and the input/output pads. The molding compound covers the chip, the die pad, the input/output pads and the first bonding wires, and exposes a first lower surface of the die pad and a second lower surface of each input/output pad. The solder resist layer is configured on the first lower surface of the die pad and has multiple openings exposing a portion of the die pad. The first solder balls are respectively configured in the openings of the solder resist layer, and the second solder balls are respectively configured on the input/output pads.

A semiconductor device includes: a semiconductor element; an island lead on which the semiconductor element is mounted; a terminal lead electrically connected to the semiconductor element; a wire connected to the semiconductor element and the terminal lead; and a sealing resin covering the semiconductor element, the island lead, the terminal lead, and the wire. The terminal lead includes a base member having an obverse surface facing in a thickness direction of the terminal lead, and a metal layer located between the obverse surface and the wire. The base member has a greater bonding strength with respect to the sealing resin than the metal layer. The obverse surface includes an opposing side facing the island lead. The obverse surface includes a first portion that includes at least a portion of the opposing side and that is exposed from the metal layer.

A power module is provided. The power module includes a first lead frame, a first die, a substrate, a second lead frame, and a second die. The first lead frame has a first part and a second part. The first die is arranged on top of the first part of the first lead frame. A first power device is formed on the first die. The substrate is arranged on top of the second part of the first lead frame. The second lead frame is arranged on top of the substrate. The second die is arranged on top of the second lead frame. A first control circuit is formed on the second die, and the first control circuit is configured to control the first power device.

A method includes providing an IC package having a lead and a die encapsulated in a mold compound. The mold compound extends from a top mold surface to a base mold surface of the IC package. The method also includes trenching the mold compound from the top mold surface to the lead to form a trench. The method further includes forming a vertical wettable flank by filling the trench with a conductive material.

A chip package having die pads with protective layers is provided. At least one protective layer is covering and arranged at a peripheral zone of at least one die pad for minimizing area of the die pad exposed outside as well as shielding and protecting the peripheral zone of the die pad. A weld zone of the die pad is not covered by the protective layer so that the weld zone of the die pad is exposed. In a crossed-over state, one of bonding wires crossing one of the die pads with a corresponding connection pad of a carrier plate will not get across a second upper space defined by the weld zone of the rest of the die pads. Thereby the one of the bonding wires can be more isolated by the protective layers on the peripheral zones of the rest of the die pads.

A semiconductor device includes: a first chip mounting portion and a second chip mounting portion adjacent to each other in a first direction; a first semiconductor chip and a third semiconductor chip adjacent to each other in a second direction and mounted on the first chip mounting portion; and a second semiconductor chip mounted on the second chip mounting portion. The third semiconductor has: one or more first transformers used to transmit a signal from the first semiconductor chip to the second semiconductor chip; and one or more second transformers used to transmit a signal from the second semiconductor chip to the first semiconductor chip. In plan view, the first and second transformers are arranged along a side facing the second semiconductor chip, and the one of more first transformers are arranged closer to the first semiconductor chip than the one of more second transformers.