A semiconductor device includes a substrate. The semiconductor device further includes a gate structure extending along a first direction. The semiconductor device further includes a first source/drain (S/D) region. The semiconductor device further includes a second S/D region separated from the first S/D region in the first direction. The semiconductor device further includes a backside via extending through the substrate, wherein the backside via is between the first S/D region and the second S/D region. The semiconductor device further includes a silicide layer between a sidewall of the first S/D region and the backside via, wherein the backside via contacts the silicide layer. The semiconductor device further includes a first dielectric spacer between the backside via and the second S/D region, wherein the backside via contacts the first dielectric spacer.

A method for manufacturing a semiconductor structure is provided. The method may include several operations. A substrate is provided, received or formed, wherein the substrate includes an epitaxial structure in a fin structure of the substrate and a metal gate structure over the fin structure. An insulating layer covering the metal gate structure is formed. A semiconductive material layer is formed over the epitaxial structure and the insulating layer, wherein a first portion of the semiconductive material layer over the epitaxial structure comprises crystalline semiconductive material, and a second portion of the semiconductive material layer over the insulating layer comprises amorphous semiconductive material. The second portion of the semiconductive material layer is removed. A semiconductor structure thereof is also provided.

A semiconductor device including a substrate, a gate oxide layer, a polysilicon layer and a metal silicide layer is provided. The gate oxide layer is formed on the substrate. The polysilicon layer is formed on the gate oxide layer. The metal silicide layer is formed on the polysilicon layer. A ratio of silicon atoms to metal atoms in the metal silicide layer is less than or equal to 2.5.

A method includes forming a source/drain region, forming a contact etch stop layer over the source/drain region, forming an inter-layer dielectric over the contact etch stop layer, forming a first contact plug in the inter-layer dielectric and the contact etch stop layer, and performing an etching process to form a trench in the inter-layer dielectric and the contact etch stop layer. The source/drain region and the first contact plug are exposed to the trench. The method further includes performing a silicide formation process to form a silicide region on a surface of the source/drain region, and etching a metal layer that is deposited on dielectric regions and in the trench. The dielectric regions are exposed at a time the silicide formation process is started. A second contact plug is formed in the trench.

The present disclosure provides a method for semiconductor fabrication. The method includes receiving a workpiece having gate structures over channel regions on a substrate and source/drain (S/D) features adjacent to the channel regions. The method then forms tungsten S/D contacts over the S/D features in a first ILD layer by a first selective bottom-up metal growth process. The method forms tungsten S/D vias over the tungsten S/D contacts in a second ILD layer by a second selective bottom-up metal growth process. And after forming the tungsten S/D vias, the method forms tungsten gate vias over the gate structures in the first and the second ILD layer. The forming of the tungsten gate vias includes forming a tungsten seed layer by physical vapor deposition (PVD), and depositing tungsten directly on horizontal and sidewall surfaces of the tungsten seed layer by chemical vapor deposition (CVD).