A semiconductor device includes: a base pattern; a first metal structure penetrating the base pattern in a first direction; at least one gate structure including a gate electrode disposed on the first metal structure in the first direction; a second metal structure penetrating the base pattern in the first direction and spaced adjacent to the first metal structure in a second direction intersecting the first direction; and a source/drain structure including at least one of a source electrode or a drain electrode disposed on the second metal structure in the first direction, wherein the first metal structure and the second metal structure are electrically separated from each other by a blocking film.

A method for manufacturing an interconnect structure includes: forming first and second etch stop layers respectively on first and second lower conductive portions, the first and second etch stop layers having different configurations; forming a dielectric layer to cover the first and second etch stop layers; performing a first etching process to form a first hole and a second hole in the dielectric layer to expose at least one of the first and second etch stop layers; performing a second etching process to form a first opening extending downwardly from the first hole and through the first etch stop layer, and to form a second opening extending downwardly from the second hole and through the second etch stop layer; and forming a first upper conductive portion in the first hole and the first opening, and forming a second upper conductive portion in the second hole and the second opening.

A device includes semiconductor channel region, source/drain regions, a source/drain contact, a first dielectric layer, a second dielectric layer, and a tungsten via. The source/drain regions are at opposite sides of the semiconductor channel region. The source/drain contact is over one of the source/drain regions. The first dielectric layer is over the source/drain contact. The second dielectric layer is over the first dielectric layer. The tungsten via extends through the first and second dielectric layers to the source/drain contact. The tungsten via includes a first portion over the source/drain contact and a second portion over the first portion. The second portion includes a tungsten sidewall laterally offset from a tungsten sidewall of the first portion, and a tungsten surface interfacing a top surface of the first dielectric layer.

An integrated circuit structure includes a first interconnect layer including a first dielectric material. The first dielectric material has a first recess therein, the first recess having a first opening. The integrated circuit structure further includes a second interconnect layer above the first interconnect layer. The second interconnect layer includes a second dielectric material that has a second recess therein. The second recess has a second opening. In an example, at least a portion of the first opening of the first recess abuts and overlaps with at least a portion of the second opening of the second recess. In an example, a continuous conformal layer is on walls of the first and second recesses, and a continuous body of conductive material is within the first and second recesses.

Techniques are provided herein for forming backend memory structures with airgaps in an interconnect region above semiconductor devices. The airgaps may be provided between conductive features, such as wordlines, to reduce parasitic capacitance. An interconnect region above a plurality of semiconductor devices includes any number of interconnect layers. A first interconnect layer includes first conductive layers (e.g., wordlines) extending in a first direction with airgaps between adjacent first conductive layers. A second interconnect layer over the first interconnect layer includes at least portions of memory cells over corresponding first conductive layers. A third interconnect layer over the second interconnect layer includes a second conductive layer (e.g., bitline) extending in a second direction over one or more of the at least portions of memory cells. The presence of airgaps between the first conductive layers allows for a tighter pitch between memory cells and reduced total energy consumption among the memory cells.

A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a first conductive layer formed over a substrate, and an air gap structure adjacent to the first conductive layer. The semiconductor device structure includes a support layer formed over the air gap structure, and a sidewall surface of the support layer is aligned with a sidewall surface of the air gap structure.

An upper surface of a plug (PL1) is formed so as to be higher than an upper surface of an interlayer insulating film (PIL) by forming the interlayer insulating film (PIL) on a semiconductor substrate (1S), completing a CMP method for forming the plug (PL1) inside the interlayer insulating film (PIL), and then, making the upper surface of the interlayer insulating film (PIL) to recede. In this manner, reliability of connection between the plug (PL1) and a wiring (W1) in a vertical direction can be ensured. Also, the wiring (W1) can be formed so as not to be embedded inside the interlayer insulating film (PIL), or a formed amount by the embedding can be reduced.

A semiconductor device structure, along with methods of forming such, are described. The semiconductor device structure includes a device, a first dielectric material disposed over the device, and an opening is formed in the first dielectric material. The semiconductor device structure further includes a conductive structure disposed in the opening, and the conductive structure includes a first sidewall. The semiconductor device structure further includes a surrounding structure disposed in the opening, and the surrounding structure surrounds the first sidewall of the conductive structure. The surrounding structure includes a first spacer layer and a second spacer layer adjacent the first spacer layer. The first spacer layer is separated from the second spacer layer by an air gap.

A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.

A semiconductor device includes a substrate, a first interlayer insulating layer disposed on the substrate, a first trench formed inside the first interlayer insulating layer, a contact plug disposed inside the first trench, a first wiring pattern disposed on the contact plug, a second wiring pattern which is disposed on the first interlayer insulating layer and spaced apart from the first wiring pattern in a horizontal direction, a second interlayer insulating layer which is disposed on the first interlayer insulating layer and surrounds each of side walls of the first wiring pattern and each of side walls of the second wiring pattern, and a first air gap formed on the contact plug inside the first trench.