One or more trench capacitor structures are included in an interconnect layer of a semiconductor device. The processing operations for forming the trench capacitor structures described herein may integrated into the processing operations for forming the interconnect layer. A plurality of columns of a bottom electrode structure of a trench capacitor structure described herein may be built up as a combination of backend conductive structures in the interconnect layer. Portions of interlayer dielectric (ILD) layers of the interconnect layer between the columns of the bottom electrode structure are removed to form trenches of the trench capacitor structure, where the columns define the trenches. The deep trenches may then be lined with a conformal insulator layer and filled with the top electrode structure of the trench capacitor structure.

An apparatus comprises a first metal feature in a first dielectric layer over a substrate, wherein a sidewall portion of the first dielectric layer is over a top surface of the first metal feature, a second dielectric layer over the first dielectric layer and a second metal feature extending through the second dielectric layer, wherein a bottom of a first portion of the second metal feature is in contact with the top surface of the first metal feature and a bottom of a second portion of the second metal feature is in contact with the sidewall portion of the first dielectric layer.

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

Various embodiments of the present disclosure are directed towards an integrated circuit (IC) in which cavities separate wires of an interconnect structure. For example, a conductive feature overlies a substrate, and an intermetal dielectric (IMD) layer overlies the conductive feature. A first wire and a second wire neighbor in the IMD layer and respectively have a first sidewall and a second sidewall that face each other while being separated from each other by the IMD layer. Further, the first wire overlies and borders the conductive feature. A first cavity and a second cavity further separate the first and second sidewalls from each other. The first cavity separates the first sidewall from the IMD layer, and the second cavity separates the second sidewall from the IMD layer. The cavities reduce parasitic capacitance between the first and second wires and hence resistance-capacitance (RC) delay that degrades IC performance.

A semiconductor structure includes a first dielectric layer, a first metallic feature over the first dielectric layer, an air gap over the first dielectric layer and adjacent to the first metallic feature, a second dielectric layer disposed above the air gap and on a sidewall of the first metallic feature, and a third dielectric layer disposed above the air gap and on a sidewall of the second dielectric layer. A lower portion of the first metallic feature is exposed in the air gap. The third and the second dielectric layers are substantially co-planar.

An integrated circuit has fuses that are selectively configurable by laser light having a wavelength incident on the fuses. A substrate of the integrated circuit has circuitry thereon. Fuses are disposed vertically above at least a portion of the circuitry. A dielectric reflector is disposed vertically above and laterally covers at least a portion of the circuitry. The dielectric reflector has a plurality of alternating dielectric layers of different refractive indices and is disposed adjacent to the fuses. The dielectric reflector is configured to reflect at least a portion of the laser light at the wavelength incident thereto.

A structure includes a substrate having a frontside and a backside. A first electrode is in a first insulator layer and is adjacent to the frontside of the substrate. The first electrode is part of a redistribution layer (RDL). A second electrode is between the substrate and the first electrode. A dielectric-filled trench in the substrate is under the first electrode and the second electrode, the dielectric-filled trench may extend fully to the backside of the substrate. The structure provides a galvanic isolation that exhibits less parasitic capacitance to the substrate from the lower electrode.

A semiconductor device includes a subtractive skip via technique in which a relatively high aspect ratio (HAR) skip via is fabricated within a lower aspect ratio (LAR) skip via opening. A metal fill is formed within the LAR skip via opening. Undesired portions of the metal fill region are removed, a retained portion or portion thereof forms the HAR skip via, and/or retained portions thereof forms multiple HAR skip vias, or the like. After forming these substrative via(s), a dielectric backfill may be formed therearound within the remaining LAR skip via opening. This backfill dielectric may be selected to reduce shorting propensities between the substrative via(s) and respective one or more wiring structures in a lower level, in a higher level, and/or the skipped level(s).

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a bottom interconnector layer positioned in the substrate; a bottom dielectric layer positioned on the bottom glue layer; an interconnector structure positioned along the bottom dielectric layer and the bottom glue layer, positioned on the bottom interconnector layer, and positioned on the bottom dielectric layer; a top glue layer conformally positioned on the bottom dielectric layer and the interconnector structure; a top dielectric layer positioned surrounding the top glue layer. A top surface of the top glue layer and a top surface of the top dielectric layer are substantially coplanar. The top dielectric layer is porous.

A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.