An integrated circuit device includes a substrate, a first transition metal dichalcogenide layer over the substrate, a dielectric layer over the first transition metal dichalcogenide layer, a first gate electrode, and a first source contact and a first drain contact. The first transition metal dichalcogenide layer has a surface roughness greater than 0.5 nm and less than 1 nm. The first gate electrode is over the dielectric layer and a first portion of the first transition metal dichalcogenide layer. The first source contact and the first drain contact are respectively connected with a second portion and a third portion of the first transition metal dichalcogenide layer. The first portion of the first transition metal dichalcogenide layer is between the second and third portions of the first transition metal dichalcogenide layer.

The present disclosure provides a semiconductor structure. The semiconductor structure includes: a substrate; a transistor on the substrate; a first dielectric layer over the transistor; a second dielectric layer over the first dielectric layer; a barrier layer extending from the second dielectric layer to the first dielectric layer; and a conductive structure separated from the second dielectric layer and the first dielectric layer by the barrier layer. The barrier layer includes: a first layer, including titanium or tantalum along inner sidewalls of the first dielectric layer and the second dielectric layer; a second layer, being an oxide of titanium or tantalum and over the first layer; and a third layer, including cobalt and over the second layer.

A method and apparatus for a gap-fill in semiconductor devices are provided. The method includes forming a metal seed layer on an exposed surface of the substrate, wherein the substrate has features in the form of trenches or vias formed in a top surface of the substrate, the features having sidewalls and a bottom surface extending between the sidewalls. A gradient oxidation process is performed in a first process chamber to oxidize exposed portions of the metal seed layer to form a metal oxide, wherein the gradient oxidation process preferentially oxidizes a field region of the substrate over the bottom surface of the features. An etch back process is performed in the first process chamber removes or reduces the oxidized portion of the seed layer. A metal gap-fill process fills or partially fills the features with a gap fill material.

Examples of an integrated circuit with an interconnect structure and a method for forming the integrated circuit are provided herein. In some examples, the method includes receiving a workpiece that includes a substrate and an interconnect structure. The interconnect structure includes a first conductive feature disposed within a first inter-level dielectric layer. A blocking layer is selectively formed on the first conductive feature without forming the blocking layer on the first inter-level dielectric layer. An alignment feature is selectively formed on the first inter-level dielectric layer without forming the alignment feature on the blocking layer. The blocking layer is removed from the first conductive feature, and a second inter-level dielectric layer is formed on the alignment feature and on the first conductive feature. The second inter-level dielectric layer is patterned to define a recess for a second conductive feature, and the second conductive feature is formed within the recess.

A layer of conductive material is formed above a bottom-most layer of interconnect structures in an interconnect layer of a semiconductor device, and the layer of conductive material is etched to define the bottom-most layer of metallization structures from the layer of conductive material. To reduce the likelihood of collapse of the free-standing metallization structures, the exposed sidewall surfaces of the free-standing metallization structures may be oxidized to form metal-oxide sidewalls for the free-standing metallization structures. The metal-oxide sidewalls may be formed using a self-aligned oxidation technique that specifically targets the sidewalls of the free-standing metallization structures for oxidation. The metal-oxide sidewalls may be formed of a metal-oxide material that increases the mechanical strength of the free-standing metallization structures, which enables the free-standing metallization structures to resist collapsing.

Metal stacks and methods of depositing a metal stack on a semiconductor substrate are disclosed. The metal stack is formed by depositing a molybdenum (Mo) layer on a semiconductor substrate. The molybdenum (Mo) layer is treated with a silane, followed by formation of a nitride layer on the molybdenum (Mo) layer. A metal stack having low resistivity is formed.

An integrated circuit device includes a transistor, a conductive contact plug, a first interconnect structure, and a conductive structure. The transistor includes a gate structure and source/drain regions at opposite sides of the gate structure. The conductive contact plug is electrically coupled to one of the gate structure and the source/drain regions. The first interconnect structure is disposed over the conductive contact plug. The conductive structure is disposed electrically coupled to the conductive contact plug by the first interconnect structure. The conductive structure includes a fill metal and a transition metal dichalcogenide liner cupping an underside of the fill metal. A bottommost position of the transition metal dichalcogenide liner is lower than a bottommost position of the fill metal.