A method of forming an electrical contact in a semiconductor structure includes performing a patterning process to form a mask on a semiconductor structure, the semiconductor structure comprising a first semiconductor region, a second semiconductor region, a dielectric layer having a first opening over the first semiconductor region and a second opening over the second semiconductor region, wherein the mask covers an exposed surface of the second semiconductor region within the second opening, performing an amorphization ion implant process to amorphize an exposed surface of the first semiconductor region within the first opening, performing a removal process to remove the mask, performing a selective epitaxial deposition process, to epitaxially form a contact layer on the exposed surface of the second semiconductor region, and performing a recrystallization anneal process to recrystallize the amorphized surface of the first semiconductor region.

There is provided a process of forming a film containing a metal element, an additional element different from the metal element and at least one of nitrogen and carbon on a substrate by performing a cycle a predetermined number of times, the cycle including non-simultaneously performing: (a) supplying a first precursor gas containing the metal element and a second precursor gas containing the additional element to the substrate so that supply periods of the first precursor gas and the second precursor gas at least partially overlap with each other; and (b) supplying a reaction gas containing the at least one of nitrogen and carbon to the substrate.

An interconnection structure includes a first dielectric layer, a second dielectric layer, first wiring patterns, and a first conductive pattern. The first wiring patterns respectively include a first penetration part that extends into a surface of the first dielectric layer, a first intervention part on the first penetration part and in the second dielectric layer, and a first connection part on the first intervention part and in the second dielectric layer. A top surface of the first intervention part is at a same level as a top surface of the first conductive pattern relative to the surface of the first dielectric layer. An angle between a sidewall of the first connection part and the top surface of the first intervention part is greater than that between a sidewall of the first penetration part and a bottom surface of the first dielectric layer.

Methods of forming high aspect ratio openings. The method comprises removing a portion of a dielectric material at a temperature less than about 0 C. to form at least one opening in the dielectric material. The at least one opening comprises an aspect ratio of greater than about 30:1. A protective material is formed in the at least one opening and on sidewalls of the dielectric material at a temperature less than about 0 C. Methods of forming high aspect ratio features are also disclosed, as are semiconductor devices.

A method for manufacturing a semiconductor device includes forming a conductive feature in a first dielectric layer; forming a second dielectric layer on the first dielectric layer; forming a trench that penetrates through the second dielectric layer, and terminates at the conductive feature; forming a contact layer in the trench and on the conductive feature; etching back the contact layer to form a first via contact feature in the trench, the first via contact feature being electrically connected to the conductive feature; and forming a second via contact feature on the first via contact feature in the trench.

The present disclosure relates to an integrated chip including a lower conductive wire within a first dielectric layer over a substrate. A second dielectric layer is over the first dielectric layer. A conductive via is over the lower conductive wire and within the second dielectric layer. A conductive liner layer lines sidewalls of the via. A barrier layer lines sidewalls of the conductive liner layer and lines sidewalls of the second dielectric layer. The conductive liner layer is laterally separated from the second dielectric layer by the barrier layer. The conductive liner layer vertically extends between sidewalls of the barrier layer from a bottom surface of the conductive via to a top surface of the lower conductive wire.

A method includes forming a first etch stop layer (ESL) over a conductive feature, forming a first dielectric layer on the first ESL, forming a second ESL on the first dielectric layer, forming a second dielectric layer on the second ESL, forming a trench in the second dielectric layer, forming a first opening in a bottom surface of the trench extending through the second dielectric layer, and forming a second opening in a bottom surface of the first opening. The second opening extends through the first dielectric layer and the first ESL. The second opening exposes a top surface of the conductive feature. The method further includes widening the first opening to a second width, filling the trench with a conductive material to form a conductive line, and filling the second opening and the first opening with the conductive material to form a conductive via.

Metal nitride diffusion barriers may be included between cobalt-based structures and ruthenium-based structures to reduce, minimize, and/or prevent intermixing of cobalt into ruthenium. A metal nitride diffusion barrier layer may include a cobalt nitride (CoN.sub.x), a ruthenium nitride (RuN.sub.x), or another metal nitride that has a bond dissociation energy greater than the bond dissociation energy of cobalt to cobalt (CoCo), and may therefore function as a strong barrier to cobalt migration and diffusion into ruthenium. Moreover, cobalt nitride and ruthenium nitride have lower resistivity relative to other materials such as titanium nitride (TiN), tungsten nitride (WN), and tantalum nitride (TaN). In this way, the metal nitride diffusion barriers are capable of minimizing cobalt diffusion and intermixing into ruthenium-based interconnect structures while maintaining a low contact resistance for the interconnect structures. This may increase semiconductor device performance, may increase semiconductor device yield, and may enable further reductions in interconnect structure size.

Some embodiments include a method in which a first stack is formed to include a metal-containing first layer, a second layer over the first layer, and a metal-containing third layer over the second layer. A first opening is formed to extend through the second and third layers. A sacrificial material is formed within the first opening. A second stack is formed over the first stack. A second opening is formed through the second stack, and is extended through the sacrificial material. First semiconductor material is formed within the second opening. A third opening is formed through the second stack and to the second layer. The second layer is removed to form a conduit. Conductively-doped second semiconductor material is formed within the conduit. Dopant is out-diffused from the conductively-doped second semiconductor material into the first semiconductor material. Some embodiments include integrated assemblies.

A device includes a gate structure, a source/drain structure, a source/drain conductor, a barrier layer, and a dielectric liner layer. The gate structure is over a semiconductor structure and includes a gate dielectric layer and at least one titanium-containing metal layer over the gate dielectric layer. The source/drain structure is adjacent the gate structure and a sidewall of the semiconductor structure. The source/drain conductor is over the source/drain structure. The barrier layer warps around the source/drain conductor. The dielectric liner layer is on a sidewall of the barrier layer. Both the dielectric liner layer and the barrier layer extend into the source/drain structure.