In an embodiment, a method includes forming a first semiconductor fin and a second semiconductor fin over a front-side of a substrate; etching a first recess in the first semiconductor fin and a second recess in the second semiconductor fin; forming a first epitaxial region in the first recess and first epitaxial nodules along sidewalls of the first recess; forming a second epitaxial region in the second recess and second epitaxial nodules along sidewalls of the second recess; flowing first precursors to remove the first epitaxial nodules; depositing an interlayer dielectric over the first epitaxial region and the second epitaxial region; etching a first opening in the interlayer dielectric to expose the first epitaxial region; forming a first epitaxial cap on the first epitaxial region and third epitaxial nodules over the interlayer dielectric; and flowing second precursors to remove the third epitaxial nodules.

An apparatus includes a backside supporting layer having a first thickness, an adhesive layer over the backside supporting layer, a metal layer over the adhesive layer, wherein the metal layer functions as a backside connector, a semiconductor substrate layer over the metal layer, wherein the semiconductor substrate active layer has a second thickness, and a plurality of front side connectors, wherein active circuits in the semiconductor substrate layer over are electrically coupled between the plurality of front side connectors and the metal layer.

A semiconductor structure includes a semiconductor fin protruding from a substrate; a gate structure engaging with the semiconductor fin. The semiconductor structure also includes an interlayer dielectric (ILD) layer disposed over the substrate and adjacent to the gate structure, where a top surface of the gate structure is below a top surface of the ILD layer; a first metal layer in direct contact with a top surface of the gate structure; a second metal layer disposed over the first metal layer, where the first metal layer is disposed on bottom and sidewall surfaces of the second metal layer, where the bottom surface of the second metal layer has a concave profile, and where the second metal layer differs from the first metal layer in composition; and a gate contact disposed over the second metal layer.

The present disclosure provides metal gap fill deposition methods on a semiconductor substrate. The methods include forming a liner layer on a surface of a feature by providing a first dosage and a second dosage of a first metal-containing precursor to a processing chamber. The feature includes a feature formed in a surface of the semiconductor substrate. The feature includes an opening that is defined by a capping layer and side walls. The side walls include a dielectric material. The liner layer is formed over the side walls and the capping layer. A metal gap fill material is deposited over the liner layer to fill the feature formed in the surface of the semiconductor substrate by providing a second metal-containing precursor and a hydrogen-containing precursor to the processing chamber.

The disclosed technology generally relates to forming thin films, and more particularly to high quality, conformal thin films using relatively low amounts of precursor gas, and methods of forming the same. In one aspect, a method of forming a thin film comprises exposing the substrate to one or more vapor deposition cycles in a reaction chamber, wherein exposing the substrate to each vapor deposition cycle comprises exposing the substrate to a first precursor and a second precursor, wherein exposing the substrate to the first precursor and the second precursor is carried out without evacuating to remove a substantial amount of either of the first precursor or the second precursor during and between exposing the substrate to the first precursor and exposing the substrate the second precursor.

An integrated circuit device includes a transistor, a conductive contact plug, a first interconnect structure, and a conductive structure. The transistor includes a gate structure and source/drain regions at opposite sides of the gate structure. The conductive contact plug is electrically coupled to one of the gate structure and the source/drain regions. The first interconnect structure is disposed over the conductive contact plug. The conductive structure is disposed electrically coupled to the conductive contact plug by the first interconnect structure. The conductive structure includes a fill metal and a transition metal dichalcogenide liner cupping an underside of the fill metal. A bottommost position of the transition metal dichalcogenide liner is lower than a bottommost position of the fill metal.

A method includes forming a first electrode, performing a first treatment process on a first oxide layer over the first electrode, wherein the first treatment process is performed using a first process gas comprising ammonia, depositing a high-k dielectric layer over the first oxide layer, forming a second electrode over the high-k dielectric layer, forming a first contact plug electrically connecting to the first electrode, and forming a second contact plug electrically connecting to the second electrode.

Integrated circuit structures including an interconnect feature without a higher-resistance liner material. In absence of a liner, metal of low resistance directly contacts an adjacent dielectric material, enabling lower resistance interconnect. Even for low-k dielectric compositions, adhesion of the metal to the dielectric material is improved through the incorporation of nitrogen proximal to the interface. Prior to deposition of the metal upon a surface of the dielectric, the surface is exposed to nitrogen species to form a nitrogen-rich compound at the surface. The metal deposited upon the surface may then be nitrogen-lean, for example a substantially pure elemental metal or metal alloy.

A device includes an active region, a gate structure, a source/drain epitaxial structure, an epitaxial layer, a metal alloy layer, a contact, and a contact etch stop layer. The gate structure is across the active region. The source/drain epitaxial structure is over the active region and adjacent the gate structure. The epitaxial layer is over the source/drain epitaxial structure. The metal alloy layer is over the epitaxial layer. The contact is over the metal alloy layer. The contact etch stop layer lines sidewalls of the source/drain epitaxial structure. The metal alloy layer is spaced apart from the contact etch stop layer.

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an apparatus includes a semiconductive region, an insulative region that is adjacent to the semiconductive region, and a conductive line that extends across the semiconductive region and at least a portion of the insulative region. The apparatus includes a contact structure that conjoins with the conductive line and that electrically couples the conductive line with the semiconductive region. The apparatus includes a footing structure that conjoins with the conductive line and that penetrates into the insulative region to anchor the conductive line with the insulative region.