A semiconductor structure and a preparation method therefor, a functional chip, and an electronic device. The method includes providing a semiconductor layer group, which includes a first dielectric layer, a semiconductor layer, a conductive structure, and an electronic element. A part of the semiconductor layer is removed from a side of a second surface of the semiconductor layer along a first direction, to expose an end face of the conductive structure away from the electronic element. A protection structure is formed on a side of the conductive structure away from the first dielectric layer, where an orthographic projection of the protection structure on the semiconductor layer covers an orthographic projection of the exposed end face of the conductive structure on the semiconductor layer. The part of the semiconductor layer is etched from the side of the second surface of the semiconductor layer along the first direction using the protection structure as a mask.

Methods of forming microelectronic devices comprise forming a dielectric layer on a substrate, the dielectric layer comprising at least one feature defining a gap including sidewalls and a bottom. The methods include forming a hardmask on the dielectric layer; selectively depositing a self-assembled monolayer (SAM) on the bottom of the gap and on the hardmask; treating the microelectronic device with a plasma to remove the self-assembled monolayer (SAM) from the hardmask; forming a barrier layer on the dielectric layer and on the hardmask; selectively depositing a metal liner on the barrier layer on the sidewall; and performing a gap fill process on the metal liner.

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.