A semiconductor structure, a method for preparing the semiconductor structure and a memory are provided. The method includes: providing a wafer in which multiple conductive pillars are formed; inverting the wafer and performing etching on a back plane of the wafer to expose each conductive pillar from the back plane of the wafer, and lengths of the multiple conductive pillars exposed to the back plane are different; depositing an insulation layer on the back plane of the wafer and the conductive pillars, and depositing a filling layer on the insulation layer, the filling layer completely covering back ends of the multiple conductive pillars; and performing polishing on the filling layer and back ends of a part of the conductive pillars, until a back end of each conductive pillar is exposed and the back ends of the multiple conductive pillars are flush with a back plane of the filling layer.

A semiconductor device comprises a substrate, a metal gate over the substrate, a poly gate over the substrate, and a source region and a drain region formed in the substrate. The poly gate is separated from the metal gate. The metal gate comprises a metal gate stack and first spacers on sidewalls of the metal gate stack, and the poly gate comprises a poly gate stack and second spacers on sidewalls of the poly gate stack. The poly gate is between the source region and the drain region.

A manufacturing method of a semiconductor structure includes following steps. A metal layer is formed above a first region and a second region of a semiconductor substrate and includes a recess above the second region. The recess is lower than a top surface of the metal layer above the first region. An oxide layer is formed on the metal layer. The oxide layer is partly formed above the first region and partly formed in the recess. A first CMP step is performed to the oxide layer. A removing rate of the oxide layer in the first CMP step is higher than that of the metal layer. A part of the oxide layer remains in the recess after the first CMP step. A second CMP step is performed after the first CMP step. The metal layer above the first and the second regions are partially removed by the second CMP step.

The present disclosure describes a method for the planarization of ruthenium metal layers in conductive structures. The method includes forming a first conductive structure on a second conductive structure, where forming the first conductive structure includes forming openings in a dielectric layer disposed on the second conductive structure and depositing a ruthenium metal in the openings to overfill the openings. The formation of the first conductive structure includes doping the ruthenium metal and polishing the doped ruthenium metal to form the first conductive structure.

A trench metal-oxide-semiconductor field-effect transistor (MOSFET) device comprises an active cell area including a plurality of superjunction trench power MOSFETs formed in an epitaxial layer. Each MOSFET includes source and body regions and a contact trench formed between first and second gate trenches. A region of the epitaxial layer between the gate trenches extends to the top surface of the epitaxial layer. An insulated gate electrode is formed in each gate trench. At least a portion of the contact trench extends from a top surface of the epitaxial layer to a depth that is shallower than the bottom of the body region.

Slurry compositions for chemical mechanical polishing, chemical mechanical polishing apparatuses using the same, and methods for fabricating a semiconductor device using the same are provided. The slurry composition for chemical mechanical polishing may include polishing particles in an amount of 0.1% to 10% by weight of the slurry composition, an oxidant in an amount of 0.1% to 5% by weight of the slurry composition, a thermo-sensitive agent in an amount of 0.01% to 30% by weight of the slurry composition. The thermo-sensitive agent may include metal nanoparticles or metal oxide nanoparticles, and water, wherein the slurry composition has a pH of 1 to 8.

A semiconductor structure includes a first dielectric layer, a first via and a second via disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer, the first via, and the second via, a first conductive line disposed on the first via and in a bottom portion of the second dielectric layer, a second conductive line disposed on the second via and in the bottom portion of the second dielectric layer, a first barrier layer extending along sidewalls and a top surface of the first conductive line, and a second barrier layer extending along sidewalls and a top surface of the second conductive line. The bottom portion of the second dielectric layer includes an air gap between the first conductive line and the second conductive line.

This invention provides a capacitor structure includes a U-shaped bottom electrode having a cap dielectric provided at its open end, a top electrode and a capacitor dielectric layer interposed between the bottom electrode and the top electrode to constitute an outer capacitor around a cylinder type solid inner capacitor, and the outer capacitor and the inner capacitor are divided by the cap dielectric. The cylinder type solid inner capacitor and the outer capacitor are fabricated separately so that the cylinder type solid inner capacitor may support its own weight to prevent its structure from being damaged during the fabrication of the capacitor.

A CMP slurry composition for patterned tungsten wafers and a method of polishing patterned tungsten wafers using the same, the CMP slurry composition includes a solvent; an abrasive; and a non-dendrimeric poly(amidoamine).