An ion implantation apparatus includes a source head including an ion source configured to generate ions, a source flange fixing a position of the source head, a source chamber spaced apart from the source head and including a source liner of ground potential, a source bushing disposed between the source flange and the source chamber, and a first insulating film covering at least a portion of an inner surface of the source bushing, the first insulating film being adjacent to the ion source, and the first insulating film including parylene.

An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.

An isolation structure, comprising: an isolation material layer, filled in a trench of a substrate; and a protection layer, having two portions extending from a topmost surface of the substrate to a top surface of the isolation material layer across boundaries of the trench, and covering opposite edges of the isolation material layer, wherein the two portions of the protection layer are laterally spaced apart from each other, and the protection layer has an etching selectivity with respect to the isolation material layer.

Multigate devices having bottom insulation and methods of fabrication thereof are disclosed. An exemplary method includes forming a first source/drain recess in a first device region, forming a second source/drain recess in a second device region, forming a first source/drain structure in the first source/drain recess, and forming a second source/drain structure in the second source/drain recess. Forming the second source/drain structure includes forming an insulator layer in the second source/drain recess, forming a mask over the first source/drain structure after performing a first nitrogen thermal treatment on the insulator layer, and forming a doped semiconductor layer over the insulator layer after performing a second nitrogen thermal treatment on the mask. The first nitrogen thermal treatment may increase a thickness and/or reduce an etch rate of the insulator layer. The first device region may be a p-type transistor region, and the second device region may be an n-type transistor region.

A semiconductor fabrication method includes providing a base containing a first area and a second area; modifying a second core material layer in the second area to form a third core material layer having an etching selectivity ratio with the second core material layer; forming a first core material layer; patterning the first core material layer and forming first core layers; forming first spacers; patterning the second and third core material layers in the second area and forming second and third core layers; forming second spacers; forming a third protective layer; patterning the third core layers through the third protective layer; patterning a target material layer through the second spacers and the third core layers and forming first and second target structures. Pitch of adjacent first target structures is less than or equal to that of adjacent second target structures. SAQP and SALELE processes are performed over the same base.

A method for forming a semiconductor structure includes providing a base with a first area and a second area; patterning a first core material layer and forming first core layers; forming first spacers; patterning a second core material layer and forming second core layers; modifying the second core layers exposed in the second area to form third core layers having an etching selectivity ratio with remaining second core layers; forming second spacers covering sidewalls of the second core layers and third core layers; and patterning a target material layer using the second spacers and third core layers as a mask and forming first target structures and second target structures. The pitch of adjacent first target structures is less than or equal to the pitch of adjacent second target structures. SAQP and SALELE processes are integrated. Redundant first target structures made by SAQP are removed without adding masks and process steps.

A method for forming semiconductor structures includes providing a base including a first area and second area; patterning a first core material layer and forming first core layers; forming first spacers; forming a first protective layer over a second core material layer in the second area; patterning the second core material layer using the first protective layer and the first spacers as a mask and forming second core layers; forming a second spacers; removing the second core layers in the first area and part of the second core layers in the second area; patterning a target material layer using the second spacers and remaining second core layers as a mask; and forming first target structures and second target structures. Pitch of adjacent first target structures is smaller than or equal to that of adjacent second target structures. Both SAQP and SALELE are implemented in the formation process over the base.

Systems and method for method of modifying an opening in a masking material layer to achieve desired critical dimensions can include forming a plurality of openings in the masking material layer, performing an ion implantation on the masking material layer to implant the masking material layer with a dopant material such that a material of the masking material layer is densified and the plurality of openings are enlarged, and directionally depositing a material layer on the masking material layer by directing a material beam at an angle relative to a top surface of the masking material layer that is selected such that the material beam is incident on sidewalls of the plurality of openings but substantially not on bottom surfaces of the plurality of openings.