A module includes an assembly of a semiconductor device die coupled to a lead frame. A board is disposed below the lead frame. The board includes a plated-through hole (PTH) aligned with an opening in the lead frame above the board. The module further includes a mold body encapsulating at least a portion of the assembly. The mold body includes a through-mold via (TMV) aligned with the opening in the lead frame and with the PTH. The PTH is physically accessible from outside the mold body through the TMV and the opening in the lead frame.

According to one embodiment, a method of manufacturing a semiconductor device includes: providing a printed circuit board that has a first surface on which a first solder resist is formed and a second surface opposite to the first surface and on which a second solder resist having a first region and a second region is formed, wherein a thickness of the second solder resist in the first region is greater than a thickness of the second solder resist in the second region in a first direction perpendicular to the second surface; placing a semiconductor chip on the first solder resist of the printed circuit board; sealing the semiconductor chip on the printed circuit board; and removing a part of the second solder resist in the first region.

A method includes providing an IC package having a lead and a die encapsulated in a mold compound. The mold compound extends from a top mold surface to a base mold surface of the IC package. The method also includes trenching the mold compound from the top mold surface to the lead to form a trench. The method further includes forming a vertical wettable flank by filling the trench with a conductive material.

A semiconductor structure is provided. The semiconductor structure includes a substrate, electronic devices, and an interconnection structure. The electronic devices are disposed on the substrate. The electronic devices includes first gate structures. The interconnection structure including a first interconnection-level conductive trace is located directly above the electronic devices. The first interconnection-level conductive trace has first openings for exposing at least one of the first gate structures.