H10W72/01935

Connection structural body with Cu—Cu bonding and roughened surface deposits

A connection structural body includes: a first connection terminal including a first opposing surface; a first roughened-surface copper metal film formed on the first opposing surface; a second connection terminal including a second opposing surface facing the first opposing surface; and a second roughened-surface copper metal film formed on the second opposing surface and bonded to the first roughened-surface copper metal film. The first roughened-surface copper metal film includes a structure in which first deposits of copper are piled over one another on the first opposing surface. The second roughened-surface copper metal film includes a structure in which second deposits of copper are piled over one another on the second opposing surface. A bonded portion of the first and second roughened-surface copper metal films includes a structure in which the first deposits and the second deposits are piled such that the bonded portion includes pores.

SEMICONDUCTOR STRUCTURE WITH BONDING STRUCTURE AND METHOD OF FORMING THE SAME

Provided is a bonding structure including a first dielectric layer, a first non-twinned metal layer, a first twinned metal layer, and a first transition layer. The first dielectric layer has a first inner sidewall defining a first via hole and a first trench on the first via hole. The first non-twinned metal layer is filled in the first via hole. The first twinned metal layer is disposed over the first non-twinned metal layer and within the first trench. The first transition layer is sandwiched between the first non-twinned metal layer and the first twinned metal layer.

SEMICONDUCTOR DEVICE AND METHOD OF FABRICATION
20260123442 · 2026-04-30 ·

A semiconductor device and method of fabrication are described. The device includes a semiconductor RFID IC base layer; a passivation layer located over the base layer and including a metal insert within the passivation layer; a repassivation layer located over the passivation layer and the metal insert; an assembly pad layer located over the repassivation layer. The device includes a first region R1 of the device, where a height of the repassivation layer is given by d.sub.1, and a region R1 is provided with an assembly pad in the assembly pad layer over the repassivation layer that has an area A.sub.1. The device includes an nth region RN of the device, where the height of the repassivation layer is given by d.sub.n, where d.sub.1>d.sub.n, and the region RN is provided with an assembly pad in the bump layer over the repassivation layer, which has an area A.sub.n, where A.sub.n>A.sub.1.

Approach to prevent plating at v-groove zone in photonics silicon during bumping or pillaring
12619038 · 2026-05-05 · ·

Embodiments disclosed herein include electronic devices and methods of forming electronic devices. In an embodiment, an electronic device comprises a die. In an embodiment, the die comprises a semiconductor substrate, a bump field over the semiconductor substrate, and a V-groove into the semiconductor substrate, wherein the V-groove extends to an edge of the semiconductor substrate. In an embodiment, the V-groove is free from conductive material. In an embodiment, the electronic device further comprises an optical fiber inserted into the V-groove.

Controlled grain growth for bonding and bonded structure with controlled grain growth

Disclosed is an element including a conductive feature at a contact surface of the element and a nonconductive region at the contact surface in which the conductive feature is at least partially embedded. The contact feature includes a conductive material and an amount of impurities at a grain boundary of the conductive material. The impurities have a non-alloying material that does not form an alloy with the conductive material at a bonding temperature.