H10W72/874

Packages with backside mounted die and exposed die interconnects and methods of fabricating the same
12550744 · 2026-02-10 · ·

A method of fabricating a semiconductor device includes forming a protective structure on at least one die on a substrate. The protective structure exposes one or more electrical contacts on a first surface of the at least one die. Respective terminals are formed on the one or more electrical contacts exposed by the protective structure. Related packages and fabrication methods are also discussed.

Electronic package and fabricating method thereof

Provided is an electronic package, in which an external connection structure is formed on a first side of a circuit structure, at least one circuit assembly electrically connected to the circuit structure and at least one electronic element electrically connected to the circuit structure are disposed on a second side of the circuit structure, and the circuit assembly and the electronic element are encapsulated by a cladding layer. The coefficients of thermal expansion (CTEs) of the circuit assembly and the cladding layer are both greater than the CTE of the circuit structure, and the CTE of the circuit structure is greater than the CTE of the external connection structure, so as to prevent the difference in CTEs between the first side and the second side of the circuit structure from being significantly changed, thereby preventing the electronic package from warpage.

Die reconstitution and high-density interconnects for embedded chips

Methods of manufacturing a sealed electrical device for embedded integrated circuit (IC) chips are described, as well as the resulting devices themselves. The sealed electrical device is created by removing material from a substrate to form a pocket in the substrate. An unencapsulated, or bare, IC chip can be placed within the pocket with connection pads of the IC chip facing outward. A gap between the IC chip and a side of the pocket can be filled with a filler. An uncured polymer can be cast over the substrate, which can be allowed to cure into a flat polymer sheet. Conductive traces can be patterned on the polymer sheet and to the connection pads of the IC chip. The conductive traces can then be coated with polymer to form a ribbon cable. Substrate can then be removed from underneath the ribbon cable, leaving substrate around the pocket to protect the IC chip.

SEMICONDUCTOR DEVICE PACKAGES
20260040980 · 2026-02-05 ·

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

SEMICONDUCTOR PACKAGE
20260041001 · 2026-02-05 ·

A semiconductor package includes a first substrate including a first interconnection structure, a first semiconductor chip, a second semiconductor chip, a second substrate, a molding layer between the first substrate and the second substrate, a plurality of conductive bumps that electrically connect the first interconnection structure to a first chip pad on a second surface of the first semiconductor chip that is opposite to the first surface of the first semiconductor chip, and a plurality of conductive wires that electrically connect the first interconnection structure to a second chip pad on a second surface of the second semiconductor chip that is opposite to the first surface of the second semiconductor chip.

SEMICONDUCTOR PACKAGE

A semiconductor package includes a first substrate having a first surface and a second surface, and having a cavity extending from the first surface to the second surface in a vertical direction, a first chip disposed in the cavity of the first substrate, a redistribution structure on the first surface of the first substrate, a second chip on the redistribution structure, a third chip spaced apart from the second chip in a horizontal direction and disposed on the redistribution structure, and a bridge chip embedded in the redistribution structure, wherein the redistribution structure includes a first redistribution pattern, a second redistribution pattern, and a third redistribution pattern.

Semiconductor package and method of manufacturing the same

The present disclosure provides a package structure and a method of manufacturing a package. The package structure includes a semiconductor die laterally encapsulated by an encapsulant, a redistribution structure and bumps. The redistribution structure is disposed on the semiconductor die and the encapsulant, and is electrically connected with the at least one semiconductor die. The bumps are disposed on the redistribution structure. The redistribution structure includes dielectric layers and metallic pattern layers sandwiched between the dielectric layers. The redistribution structure includes metallic pads on an outermost dielectric layer of the dielectric layers, and the outmost dielectric layer has undercut cavities beside the metallic pads.

FAN-OUT WAFER LEVEL PACKAGING UNIT
20260076220 · 2026-03-12 ·

A fan-out wafer-level packaging (FOWLP) unit having a substrate, at least one chip, a dielectric layer, at least one conductive circuit, and an outer protective layer is provided. The chip includes a die, chip conductive circuits, a chip dielectric layer, chip bonding pads, a first chip surface, and a second chip surface. The die is electrically connected with the outside through the die pad. The conductive circuits are formed by a metal paste filled into at least one slot of the dielectric layer and grinding of the metal paste. The conductive circuits form a bonding pad in each of openings of the outer protective layer. The chip is electrically connected to the outside through the bonding pads located around a chip area on the second chip surface of the chip. Thereby problems of the FOWLP module available now including higher manufacturing cost and less environmental benefit can be solved.

WORKPIECE HANDLING APPARATUS

A workpiece handling apparatus includes a workpiece chuck, and a robotic device. The workpiece chuck is for holding a workpiece thereon, wherein the workpiece chuck includes a porous supporting platform, a gas permeable buffer layer covering a supporting surface of the porous supporting platform, and a vacuum system in gas communication with the porous supporting platform and the gas permeable buffer layer. The robotic device is movably disposed over the workpiece chuck for picking up the workpiece and placing the workpiece on the gas permeable buffer layer.

Pad design for reliability enhancement in packages

A package includes a corner, a device die, a molding material molding the device die therein, and a plurality of bonding features. The plurality of bonding features includes a corner bonding feature at the corner, wherein the corner bonding feature is elongated. The plurality of bonding features further includes an additional bonding feature, which is non-elongated.