Technologies for conformal power delivery structures near high-speed signal traces are disclosed. In one embodiment, a dielectric layer may be used to keep a power delivery structure spaced apart from high-speed signal traces, preventing deterioration of signals on the high-speed signal traces due to capacitive coupling to the power delivery structure.

An optical transmission device includes a substrate that includes a first surface, a switch-integrated-circuit chip, a first connector coupled to the chip, a second connector provided between the chip and the first connector, a first optical-module coupled to the first connector, a second optical-module coupled to the second connector, and a cooling plate that includes a first cooling-unit that cools the chip, and a second cooling-unit that cools the first and second optical-modules, wherein the second cooling-unit includes second and third surfaces, the second and third surfaces are inclined such that distances between the first surface and the second and third surfaces reduce as distances between the chip and the second and third surfaces reduce, respectively, wherein the second surface is closer to the first surface than the third surface, wherein the first and second optical-modules are provided over the second and third surfaces, respectively.

A semiconductor structure and a manufacturing method thereof are provided. A semiconductor structure includes a first nitride-containing layer on a side of a carrier substrate, first semiconductor devices thermally coupled to the first nitride-containing layer, a first interconnect structure physically and electrically coupled to first sides of the first semiconductor devices, and a first metal-containing dielectric layer bonding the first nitride-containing layer to the first interconnect structure. A thermal conductivity of the first nitride-containing layer is greater than a thermal conductivity of the first metal-containing dielectric layer.

Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

Integrated circuit dies, systems, and techniques, are described herein related to single conductivity type transistor circuits operable at low temperatures. A system includes a functional circuit block of an integrated circuit die having a number of non-planar transistors all of the same conductivity type. The system further includes cooling structure integral to the integrated circuit die, coupled to the integrated circuit die, or both. The cooling structure is operable to remove heat from the integrated circuit die to achieve an operating temperature at the desired low temperature.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die having a surface; a template structure having a first surface and an opposing second surface, wherein the first surface of the template structure is coupled to the surface of the first die, and wherein the template structure includes a cavity at the first surface and a through-template opening extending from a top surface of the cavity to the second surface of the template structure; and a second die within the cavity of the template structure and electrically coupled to the surface of the first die by interconnects having a pitch of less than 10 microns between adjacent interconnects.

A semiconductor package including a ring structure with one or more indents and a method of forming are provided. The semiconductor package may include a substrate, a first package component bonded to the substrate, wherein the first package component may include a first semiconductor die, a ring structure attached to the substrate, wherein the ring structure may encircle the first package component in a top view, and a lid structure attached to the ring structure. The ring structure may include a first segment, extending along a first edge of the substrate, and a second segment, extending along a second edge of the substrate. The first segment and the second segment may meet at a first corner of the ring structure, and a first indent of the ring structure may be disposed at the first corner of the ring structure.

A semiconductor package includes a package substrate, a power module on a first surface of the package substrate, a connector on the first surface of the package substrate, the connector being horizontally spaced apart from the power module, a first semiconductor chip on a second surface of the package substrate opposite to the first surface, and a first heat radiator on the second surface of the package substrate, the first heat radiator covering the first semiconductor chip. The first semiconductor chip vertically overlaps the power module, and the first semiconductor chip is electrically connected through the package substrate to the power module.

The present disclosure relates to methods and apparatus for forming a thin-form-factor semiconductor device package. In certain embodiments, a glass or silicon substrate is patterned by laser ablation to form structures for subsequent formation of interconnections therethrough. The substrate is thereafter utilized as a frame for forming a semiconductor device package, which may have one or more embedded double-sided dies therein. In certain embodiments, an insulating layer is formed over the substrate by laminating a pre-structured insulating film thereon. The insulating film may be pre-structured by laser ablation to form structures therein, followed by selective curing of sidewalls of the formed structures.

A semiconductor device package includes an interconnect structure with a first surface having at least one die thereon and a second surface that is opposite the first surface and is configured to be coupled to an external device. A protective structure on the first surface of the interconnect structure exposes a heat dissipating surface facing away from the interconnect structure in one or more directions. Related devices and fabrication methods are also discussed.