A package comprising a metallization portion; an integrated device comprising a plurality of pillar interconnects, wherein the integrated device is coupled to the metallization portion through the plurality of pillar interconnects; and an encapsulation layer at least partially encapsulating the integrated device, wherein the encapsulation layer is coupled to the metallization portion.

A semiconductor device includes a substrate, a first electrode and a second electrode. The semiconductor device includes a MOSFET that has the first electrode as a drain electrode and the second electrode as a source electrode. The first electrode has a layer region provided on a first main surface and a first region extending from the first main surface into the substrate in a first direction from the first electrode to the second electrode. A lower surface of the first electrode protrudes in a direction opposite to the first direction.

Capacitive couplings in a direct-bonded interface for microelectronic devices are provided. In an implementation, a microelectronic device includes a first die and a second die direct-bonded together at a bonding interface, a conductive interconnect between the first die and the second die formed at the bonding interface by a metal-to-metal direct bond, and a capacitive interconnect between the first die and the second die formed at the bonding interface. A direct bonding process creates a direct bond between dielectric surfaces of two dies, a direct bond between respective conductive interconnects of the two dies, and a capacitive coupling between the two dies at the bonding interface. In an implementation, a capacitive coupling of each signal line at the bonding interface comprises a dielectric material forming a capacitor at the bonding interface for each signal line. The capacitive couplings result from the same direct bonding process that creates the conductive interconnects direct-bonded together at the same bonding interface.

A package substrate according to the present disclosure includes a package substrate, an interposer disposed over the package substrate, a photonic die disposed over the interposer, a memory structure disposed over the interposer and including a controller die, a system die disposed over the interposer and partially overlapping with the photonic die and the controller die, and a lid covering the system die, the memory structure, and photonic die. The system die includes micro bumps extending from a bottom surface of the system die to a top surface of the controller die.

An electronic device includes a leadframe where the leadframe includes a first set of leads, a second set of leads, and conductive pads. A heat sink is attached to the conductive pads. The heat sink includes a pair of heat sink pads separated by a gap, and a die attach pad. The die attach pad has a semi-circular shape and is connected to an end of each of the pair of heat sink pads to form a U-shape. The die attach pad further includes an airgap prevention feature. A die is attached to the heat sink and wire bonds connect the die to the leadframe. A mold compound encapsulates the heat sink, the die, and the wire bonds.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A method of manufacturing a semiconductor device includes reducing a thickness of a device wafer bonded to a carrier wafer, wherein the device wafer includes a device, a portion of the carrier wafer beyond the device, in a plan view, is called a non-bonding area, and a portion of the carrier wafer overlapping the device, in the plan view, is called a device area. The method further includes performing an etching process on the non-bonding area of the carrier wafer, wherein the etching process is performed completely outside the device area of the carrier wafer.

A hollow package includes a device substrate; a lid substrate provided above the device substrate; a first sealing ring provided on an upper surface of the device substrate; a second sealing ring provided on a lower surface of the lid substrate so as to face the first sealing ring; a seal layer that bonds the first sealing ring and the second sealing ring; and a functional element provided in a hollow portion surrounded by the device substrate, the lid substrate, the first sealing ring, the second sealing ring, and the seal layer, wherein the first sealing ring or the second sealing ring has a corner portion in a planar view, and the first sealing ring or the second sealing ring has a recess, which is recessed in a direction perpendicular to the upper surface of the device substrate, locally formed in a portion including the corner portion.

The present disclosure describes a bonded semiconductor structure and a method of forming the bonded semiconductor structure. The bonded semiconductor structure includes first and second substrates bonded with a bonding structure. The bonding structure provides high thermal conductivity and high bonding strength between the first and second substrates. The bonding structure includes bonding layers and adhesion layers, with the bonding layers including titanium oxide and the adhesion layers including titanium nitride. The method includes forming a first adhesion layer on the first substrate and a second adhesion layer on the second substrate. The method also includes forming a first bonding layer on the first adhesion layer and a second bonding layer on the second adhesion layer. The method further includes bonding the first and second substrates by bonding the first and second bonding layers together.

An electrically non-conducting film (109) comprising an oligomer comprising an arylene or heteroarylene repeating unit is disposed between a chip (105), e.g. a flip-chip, and a functional layer (101), e.g. a printed circuit board, electrically connected to the chip by electrically conducting interconnects (107). The oligomer may be crosslinked.