A semiconductor structure and a method of fabricating the semiconductor structure are disclosed. The semiconductor structure includes: a carrying layer, a barrier layer, a solder layer and an adhesive layer. The barrier layer is located on the surface of the carrying layer, and there are openings in the barrier layer. The barrier layer includes multiple sub-barrier layers in a stack. The multiple sub-barrier layers respectively form a plurality of steps in the opening, and the heights of the plurality of steps decrease sequentially in a direction from outside of the opening to inside of the opening. A solder layer and an adhesive layer are located in the opening, and the adhesive layer covers the solder layer.

Provided is a semiconductor package, including a lower redistribution layer structure including a lower redistribution layer, a lower semiconductor chip on the lower redistribution layer structure, the lower semiconductor chip connected to the lower redistribution layer, a sealing member on the lower semiconductor chip and the lower redistribution layer structure, a conductive post penetrating the sealing member, the conductive post connected to the lower redistribution layer, and an upper redistribution layer structure on an upper surface of the sealing member and an upper surface of the conductive post, the upper redistribution layer structure including an upper insulation layer and an upper redistribution layer, wherein a sidewall of the conductive post has a first uneven portion, and an upper surface of the conductive post has a second uneven portion, a roughness of the second uneven portion being different from a roughness of the first uneven portion.

The present technology pertains to a packaged microchip that includes an integrated cold plate. The packaged microchip includes a substrate and a die, which can be a semiconductor chip on which an integrated circuit has been fabricated. The die has a thermal-interface surface on which a thermal interface material (TIM) is provided. The integrated cold plate is fixed to the substrate. The cold plate has a die surface and a heat-dissipating surface. The die surface contacts the TIM such that the TIM is sandwiched between the die and the heat-removal member. The heat-removal member is monolithic and is configured to remove heat from the die via heat transfer from the heat-removal member to a fluid.