An n-type metal oxide semiconductor transistor includes a gate structure, two source/drain regions, two amorphous portions and a silicide. The gate structure is disposed on a substrate. The two source/drain regions are disposed in the substrate and respectively located at two sides of the gate structure, wherein at least one of the source/drain regions is formed with a dislocation. The two amorphous portions are respectively disposed in the two source/drain regions. The silicide is disposed on the two source/drain regions, wherein at least one portion of the silicide overlaps the two amorphous portions.

Provided is a semiconductor device including: a buffer region having a doping concentration higher than a bulk donor concentration; a first low-concentration hydrogen peak in the buffer region; a second low-concentration hydrogen peak in the buffer region closer to a lower surface than the first low-concentration hydrogen peak; a high-concentration hydrogen peak in the buffer region closer to the lower surface than the second low-concentration hydrogen peak, the high-concentration hydrogen peak having a hydrogen chemical concentration higher than that of the second low-concentration hydrogen peak; and a flat region including a region between the two low-concentration hydrogen peaks and a region including the second low-concentration hydrogen peak, and having a doping concentration higher than a bulk donor concentration, an average value of the doping concentration being equal to or smaller than a local minimum value of a doping concentration between the second low-concentration hydrogen peak and the high-concentration hydrogen peak.

A semiconductor device includes: a substrate including (i) a first active region comprising a plurality of unit cells, and (ii) a peripheral area surrounding at least a portion of the first active region; a gate frame comprising (i) a first portion in a wiring region and extending along a first direction, (ii) a second portion extending from one side of the first portion along a second direction crossing the first direction and connected to a first end of at least a portion among the plurality of unit cells, and (iii) a third portion extending from the first side along the second direction and connected to a second end of at least a portion among the plurality of unit cells; a first gate runner on the first portion of the gate frame and the second portion of the gate frame; and a second gate runner on the third portion.

A method of forming a semiconductor device includes forming a fin on a substrate, the fin comprising alternately stacked first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form a plurality of spaces each between adjacent two of the second semiconductor layers, implanting oxygen into the second semiconductor layers, and forming a gate structure wrapping around the second semiconductor layers.

A method of manufacturing an electronic device includes a) forming, in a semiconductor substrate first doped regions of a first type and second doped regions of a second type; b) depositing a dielectric layer on the upper surface of the substrate; c) after step b), forming first and second openings in dielectric layer to expose the first and second regions; d) implanting non-doping ions in the second regions to amorphize an upper portion of the second regions; e) after steps c) and d), filling the first and second openings with doped monocrystalline or polycrystalline silicon of the first type; and f) performing a thermal anneal of the device to recrystallize said upper portion of the second regions and generate crystal defects in a space charge region of a p-n junction formed at the interface between the vias and the second regions.

A semiconductor device includes a chip formed by a wide bandgap semiconductor and having a principal surface on which a semiconductor region of a first conductivity type is formed, a base impurity region of a second conductivity type formed in a surface layer portion of the semiconductor region, a first impurity region formed in a surface layer portion of the base impurity region, and a second impurity region of a conductivity type opposite to that of the first impurity region formed in the surface layer portion of the base impurity region, the second impurity region being adjacent to the first impurity region in a first direction, wherein the second impurity region is formed in a band shape extending in a second direction orthogonal to the first direction, and includes a projection portion selectively protruding toward the first impurity region in the first direction.

Disclosed semiconductor structures include a stack of III-V semiconductor layers and a III-V semiconductor device and a silicon device on the stack. The III-V semiconductor device includes, among other components, a barrier layer above and immediately adjacent to a III-V semiconductor surface at the top of the stack in a first area. The silicon device includes, among other components, a silicon-based layer above and immediately adjacent to the same III-V semiconductor surface at the top of the stack in a second area. Thus, the barrier layer and the silicon-based layer are at the same level above the substrate. Optionally, an isolation well can be within the stack adjacent to the III-V semiconductor surface in the second area (e.g., to electrically isolate the III-V semiconductor device from the silicon device). Also disclosed are methods of forming the semiconductor structures.

A method for manufacturing a semiconductor stack structure with ultra thin die includes manufacturing semiconductor wafers, wherein a stop layer structure formed by ion implantation is formed in the semiconductor substrate, and the conductive structures are formed to connect the dielectric stop layer and the redistribution layer of the semiconductor wafers. A bonding layer with conductive pillars is formed on the redistribution layer of another semiconductor wafer, and die sawing is performed to form multiple batches of dies. The bonding layers of a batch of dies is bonded to the exposed dielectric stop layers of the semiconductor wafers by hybrid bonding. An encapsulant covers the batch of dies, and part of the encapsulant, part of the semiconductor substrate and part of the stop layer structure of each die are removed to expose the dielectric stop layer and conductive structures of this batch of dies for bonding next batch of dies.

Methods of processing a substrate are disclosed herein which include treating a surface of a first portion of the substrate to produce a treated substrate having a treated first portion and a second portion, wherein a bonding speed of the treated first portion to another substrate is different than a bonding speed of the second portion to the other substrate. A method of bonding a first substrate to a second substrate is also disclosed.