A method of manufacturing a semiconductor package may include disposing, in a lower mold, a substrate strip in which a plurality of semiconductor chips are arranged in a horizontal direction, providing, in an upper mold, a release film to which a first encapsulant is attached, allowing the upper mold and the lower mold to be proximate to each other such that a first encapsulant is adjacent to an upper surface of each of the plurality of semiconductor chips, injecting a second encapsulant into a space between the upper mold and the lower mold, heating the first encapsulant and the second encapsulant to form a molded structure including a first encapsulating layer and a second encapsulating layer, allowing the upper mold and the lower mold to be spaced from each other such that the molded structure is separated from the release film, and cutting the molded structure.

A semiconductor package includes; a redistribution wiring layer, a controller chip centrally disposed on the redistribution wiring layer, a first sealant disposed on the redistribution wiring layer, wherein the controller chip is buried in the first sealant, through vias connected to the redistribution wiring layer through the first sealant, and a sub-package disposed on an upper surface of the first sealant. The sub-package may include a first stack structure disposed to one side of the controller chip on the upper surface of the first sealant and including vertically stacked chips, a second stack structure disposed to another side of the controller chip on the upper surface of the first sealant adjacent to the first stack structure in a first horizontal direction and including vertically stacked chips, and a second sealant sealing the first stack structure and the second stack structure.

Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first die, having a first surface and an opposing second surface with conductive contacts, in a first layer; a first material surrounding the first die and extending along a thickness of the first die from the second surface, and wherein the first material includes first particles having an average diameter between 200 and 500 nanometers; a second material surrounding the first die and extending along the thickness of the first die from the first surface, and wherein the second material includes second particles having an average diameter between 0.5 and 12 microns; an interface portion, between the first and second materials, including the first and second particles; and a second die, in a second layer on the first layer, electrically coupled to the conductive contacts on the first die.

A semiconductor package includes a lower redistribution wiring layer; and a first semiconductor device on the lower redistribution wiring layer, the first semiconductor device being connected to the lower redistribution wiring layer via conductive bumps, wherein the lower redistribution wiring layer includes: a first redistribution wire in a first lower insulating layer; an insulating structure layer having an opening that exposes a portion of the first redistribution wire, the insulating structure layer including a first photosensitive insulating layer, a light blocking layer on the first photosensitive insulating layer, and a second photosensitive insulating layer on the light blocking layer; a second redistribution wire in the opening of the insulating structure layer, the second redistribution wire including a redistribution via contacting the first redistribution wire, and a redistribution line stacked on the redistribution via; and bonding pads bonded to the conductive bumps and electrically connected to the second redistribution wire.

A semiconductor device includes: a baseplate; an insulating substrate on the baseplate; a semiconductor element on the insulating substrate; a case bonded to the baseplate by an adhesive, the case surrounding a space in which the semiconductor element is positioned; and an encapsulating material filling the space surrounded by the case, in which, the case includes a claw, the claw includes: a protrusion protruding from an inner wall surface of the case; and a hook inclined from the protrusion, a space being sandwiched between the hook and the inner wall surface of the case.

An encapsulated integrated circuit includes an integrated circuit (IC) die. An encapsulation material encapsulates the IC die. Within the encapsulation material, a phononic bandgap structure is configured to have a phononic bandgap with a frequency range approximately equal to a range of frequencies of thermal phonons produced by the IC die when the IC die is operating.

A die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector comprises a seed layer and a conductive post on the seed layer. The protection layer laterally covers the connector. The passivation layer is disposed between the protection layer and the conductive pad. The conductive post is separated from the passivation layer and the protection layer by the seed layer.

A power conversion apparatus is a semiconductor apparatus including: a semiconductor module in which a semiconductor element and the heat exchanger plate connected to the semiconductor element are molded and sealed with resin; and a thermal conductive material having a semisolid shape disposed between the semiconductor module and a cooling member that cools the semiconductor module, in which a thickness of the resin between the thermal conductive material and the heat exchanger plate is larger than a thickness of the thermal conductive material.

A resin composition includes a compound having an oxazoline group, a phenol type curing agent, and an inorganic filler.

A method of forming a semiconductor package includes forming, on a first semiconductor chip, a plurality of inner connection terminals and a preliminary underfill covering the plurality of inner connection terminals, stacking the first semiconductor chip on a lower structure such that the preliminary underfill is bonded between the first semiconductor chip and the lower structure, and curing the preliminary underfill using a laser bonding process, thereby forming a first underfill, and reflowing the plurality of inner connection terminals during a formation of the first underfill through the curing of the preliminary underfill.