An electronic component including a first device die hybrid bonded to a carrier, an encapsulant encapsulating side surfaces of the first device die and a cover element disposed over directly bonded to a top surface of the first device die. The encapsulant comprises particles embedded therein, and wherein an interface between a top surface of the encapsulant and a bottom surface of the cover element lacks ground particles

A resin composition for molding includes an epoxy resin, a curing agent containing an active ester compound, an inorganic filler, and a porous polymer particle.

A method of manufacturing a packaging substrate according to the present disclosure comprises a preparation step of preparing a preliminary substrate including a glass core on which a device portion including a device is mounted; and an encapsulation layer forming step of manufacturing the packaging substrate by forming an encapsulation layer surrounding at least a portion of the device portion with an encapsulation layer-forming composition. The glass core comprises a cavity portion that is a space formed by being recessed on an upper surface side of the glass core. The device portion is disposed in the cavity portion. A viscosity of the encapsulation layer-forming composition at 25 C. is 12,000 cps to 38,000 cps.

In this case, it is possible to suppress occurrence of voids in the encapsulation layer, and it is possible to suppress occurrence of defects such as the glass core and the encapsulation layer which may occur in the manufacturing process.

A semiconductor package according to some embodiments includes a first redistribution layer including a plurality of redistribution patterns, a semiconductor chip on the first redistribution layer, a second redistribution layer including a plurality of redistribution patterns on the semiconductor chip, and a plurality of conductive posts extending in a first direction between the first redistribution layer and the second redistribution layer to connect the first redistribution layer and the second redistribution layer, wherein each of the plurality of conductive posts includes a first portion and a second portion on the first portion, and the second portion includes at least one first space positioned inside the second portion and at least one second space connecting the at least one first space to an outer side surface of the second portion.

A semiconductor encapsulation method, comprising: forming a protection layer on a front side of a chip to be encapsulated; arranging said chip, with the protection layer being formed on the front side thereof, on a carrier plate, wherein the front side of said chip faces upwards and a back side thereof faces the carrier plate; and encapsulating, on the carrier plate, said chip and the protection layer to form a plastic encapsulation layer. Further provided is a semiconductor encapsulation structure.

An electronic device includes a three-dimensionally non-planar mold body defining at least part of one of a non-planar side surface and an opposed non-planar side surface of the electronic device, an electrically conductive structure provided on one of the non-planar side surface and the opposing non-planar side surface, and at least one electric entity at least partially inside of the three-dimensionally non-planar mold body.

An electronic package is provided which includes a continuous stiffener element (i.e., frame) located around a semiconductor die. The continuous stiffener element has a coefficient of thermal expansion (CTE) that closely matches the CTE of a carrier substrate that is located beneath the semiconductor die. The closely matched CTA between the continuous stiffener element and the carrier substrate reduced warpage in an electronic package containing the same. A molding component can be disposed between the continuous stiffener element and the semiconductor die. The electronic package having the reduced warpage can be used as a component of an electronic packaging structure.

A semiconductor package includes a first interconnect component, a second interconnect component and a third encapsulant. The first interconnect component includes a first encapsulant. The second interconnect component is laterally spaced apart from the first interconnect component and includes a second encapsulant. The third encapsulant laterally encapsulates the first interconnect component and the second interconnect component. The first encapsulant includes a first filler having a first average size, and the second encapsulant includes a second filler having a second average size different from the first average size.

A metal oxide particle material contains a metal oxide as a main component and has: a D50 of 1.0 m or more and 5.0 m or less, the D50 being obtained by measuring a laser diffraction particle size distribution; a specific surface area of 1.0 m.sup.2/g or more and 30 m.sup.2/g or less; a coarse particle content of 300 ppm or less, the coarse particle content being a content of coarse particles having a particle diameter of 5 m or more; and a hollow particle content of 4000 particles/10 mg or less, the hollow particle content being a content of hollow particles having a particle diameter of 5 m or more. When a resin material is filled with the metal oxide particle material at a solid concentration of 60% by mass, a resultant resin composition has a viscosity of 170 Pa.Math.s or less (at a shear velocity of 1 s.sup.1).