In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

A semiconductor package including an interposer substrate, first to third semiconductor chips on the interposer substrate to face each other, an underfill part between each of the first to third semiconductor chips and the interposer substrate, a first side-fill part extending upward from a lower end of side walls of the first to third semiconductor chips, and a second side-fill part between the side walls of the first to third semiconductor chips and extending from the first side-fill part to an upper end of the side walls of the first to third semiconductor chips may be provided.

A stacked package structure and a manufacturing method thereof are provided. The stacked package structure includes an upper redistribution layer, a first chip, and an upper molding layer. The first chip is disposed on the upper redistribution layer and is electrically connected to the upper redistribution layer. The upper molding layer is disposed on the first chip and the upper redistribution layer, and is configured to package the first chip. The upper molding layer includes a recess, the recess is recessed relative to a surface of the upper molding layer away from the upper redistribution layer, and the recess is circumferentially formed around a periphery of the upper molding layer.

In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

In some examples, a sensor package includes a semiconductor die having a sensor; a mold compound covering a portion of the semiconductor die; and a cavity formed in a top surface of the mold compound, the sensor being in the cavity. The sensor package includes an adhesive abutting the top surface of the mold compound, and a semi-permeable film abutting the adhesive and covering the cavity. The semi-permeable film is approximately flush with at least four edges of the top surface of the mold compound.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.

A semiconductor structure includes a first back-end-of-line region coupled to a first side of a front-end-of-line region, a second back-end-of-line region coupled to a second side of the front-end-of-line region, and a thermally conducting region at least partially surrounding a perimeter of the front-end-of-line region, the first back-end-of-line region and the second back-end-of-line region.

A semiconductor package may include a substrate including a connection circuit, a redistribution structure, and a chip structure on the redistribution structure. The redistribution structure may include a rear redistribution layer electrically connected to the connection circuit, a first semiconductor chip between rear and front redistribution portions and electrically connection to a front redistribution layer of the front redistribution portion, a first molded portion covering at least a portion of the first semiconductor chip, and a first through-via passing through the first molded portion and electrically connecting the front and the rear redistribution layers. The chip structure may include a wiring portion having a wiring layer electrically connected to the front redistribution layer, second and third semiconductor chips on the wiring portion and electrically connected to the wiring layer, and a second molded portion covering at least a portion of each of the second and third semiconductor chips.

A chip scale semiconductor package comprises a silicon layer, a back side metal layer, and a plurality of front side pads. Each of the plurality of front side pads comprises a respective copper member and a respective solder member. A method comprises the steps of: providing a wafer; grinding the back side of the wafer forming a peripheral ring; applying a metallization process to a grinded surface; removing the peripheral ring; forming a front side seed layer; forming a front side photoresist layer; applying a photolithography process; applying a front side copper plating process; applying a front side solder plating process; stripping the front side photoresist layer; etching the front side seed layer; and applying a singulation process.

A chip package and a method of manufacturing the same are provided. The chip package includes at least one insulating protective layer disposed on a periphery of a surface of a seed layer correspondingly. A plurality of insulating protective layers is arranged at the seed layer of a plurality of rectangular chips of a wafer and located corresponding to a plurality of dicing streets. Thereby cutting tools only cut the insulating protective layer, without cutting a thick metal layer during cutting process. The insulating protective layer is formed on a periphery of the thick metal layer of the chip package after the cutting process.