A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

A metal bump containing structure is provided which has a substantially flat top surface and enhanced coplanarity with other like metal bump containing structures. The metal bump containing structures include a metal bump having a curved top surface, and a first metal liner located along an outermost sidewall and present at least partially on the curved top surface of the metal bump.

A structure including a substrate having a conductive pad and a connecting structure disposed on the conductive pad and electrically connected to the conductive pad. The connecting structure includes a first metallic layer disposed on the conductive pad, a first intermetallic compound layer disposed on the first metallic layer, a second intermetallic compound layer disposed on the first intermetallic compound layer and a second metallic layer disposed on the second intermetallic compound layer. The first metallic layer comprises copper. The first intermetallic compound layer comprises a first intermetallic compound. The second intermetallic compound layer comprises a second intermetallic compound different from the first intermetallic compound. The second metallic layer comprises tin. The first intermetallic compound contains copper, tin and one of nickel and cobalt.

A semiconductor device and a method for fabricating a semiconductor are described. The semiconductor device includes two modules, each module including two tiers, each tier including (i) a passive die including through-silicon vias (TSVs) arranged side-by-side laterally with a core die and (ii) bumps coupling the TSVs and an overhang portion of the core die of a second tier to the TSVs the first tier, the first module further including a bottom redistribution layer (RDL) on which the first second tier of the first module is disposed and a top RDL disposed on the second tier of the first module, the bottom RDL coupled to the bumps disposed on the first tier of the first module while the top RDL configured to couple the bumps of the first tier of the second module to the TSVs of the second tier of the first module in a one-to-one manner.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

Provided is a non-electroconductive flux capable of enhancing productivity and impact resistance of a connected structure to be obtained and suppressing occurrence of solder flash. The non-electroconductive flux according to the present invention contains an epoxy compound, an acid anhydride curing agent, and an organophosphorus compound.

A semiconductor package may include a first substrate; a second substrate on the first substrate; at least one chip structure on the second substrate; connection bumps below the first substrate; first bump structures between the first substrate and the second substrate; and second bump structures between the at least one chip structure and the second substrate, wherein each of at least a portion of the first bump structures and the each of at least a portion of the second bump structures includes a pillar bump, a solder ball connecting the pillar bump to one of the upper pads or upper terminals, and a barrier film at least partially covering a side surface of the pillar bump, and wherein a thickness of the barrier film decreases in a direction perpendicular to the side surface of the pillar bump in a portion adjacent to the solder ball.

A chip-size-package type semiconductor device includes a semiconductor layer, pads, and metal redistributions that are located above a top surface of the semiconductor layer and each of which is connected to one or more pads. The metal redistributions include first metal redistributions each of which includes a first portion and a second portion contained within the first portion in a plan view, the second portion being located above the first portion and having an area smaller than an area of the first portion in the plan view. Each of the first metal redistributions includes one or more line-shaped bends in a boundary portion between the first portion and the second portion on a surface of the first metal redistribution, the one or more line-shaped bends each having an interior angle of at least 180 degrees in a cross section of the first metal redistribution.

An electronic device according to the present disclosure includes a semiconductor substrate, a chip, and a bump. The chip has a thermal expansion coefficient different from that of the semiconductor substrate. The bump connects the connection pads provided on the opposing principal surfaces of the semiconductor substrate and the chip. The bump has a porous metal layer and a metal film. The metal film is provided on at least one of a portion between the connection pad provided on the semiconductor substrate and the porous metal layer and a portion between the connection pad provided on the chip and the porous metal layer, and on the side surfaces of the porous metal layer.

In some embodiments, an interconnection structure can electrically and physically couple a first semiconductor die and a second semiconductor die. The interconnection structure can include a first portion at the first semiconductor die and a second portion at the second semiconductor die. The first portion can include a first conductive pillar with a concave bonding surface, a first annular barrier layer, and a first annular solder layer. The first annular barrier layer can surround a sidewall of the first conductive pillar, and the first annular solder layer can surround the first barrier layer. The second portion can include a second conductive pillar having a convex bonding surface, the convex bonding surface coupled to the concave bonding surface. The second interconnection structure can further include a second annular solder layer surrounding a second annular barrier layer surrounding the second conductive pillar.