Methods and apparatus of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

Methods of hybrid bonding with inspection are provided herein. In some embodiments, a method of hybrid bonding with inspection includes: cleaning a substrate via a first cleaning chamber and a tape frame having a plurality of chiplets via a second cleaning chamber; inspecting, via a first metrology system, the substrate for pre-bond defects in a first metrology chamber and the tape frame for pre-bond defects in a second metrology chamber; bonding one or more of the plurality of chiplets to the substrate via a hybrid bonding process in a bonder chamber to form a bonded substrate; and performing, via a second metrology system different than the first metrology system, a post-bond inspection of the bonded substrate via a third metrology chamber for post-bond defects.

A bonding apparatus includes a chuck table, a gantry frame, a bond head and a gas supplying mechanism. The chuck table is configured to support a semiconductor wafer. The gantry frame is disposed over the chuck table. The bond head is movably installed on the gantry frame, wherein the bond head is configured to pick up a semiconductor chip from a support structure, and for moving the semiconductor chip towards the chuck table for bonding to the semiconductor wafer. The gas supplying mechanism is configured to supply a bonding gas to the semiconductor wafer during the bonding of the semiconductor chip.

Disclosed herein are methods for direct bonding. In some embodiments, a direct bonding method comprises preparing a first bonding surface of a first element for direct bonding to a second bonding surface of a second element; and after the preparing, providing a protective layer over the prepared first bonding surface of the first element, the protective layer having a thickness less than 3 microns.

A bonded assembly includes a first semiconductor die containing first semiconductor devices and a first bonding pad embedded within a first silicon oxide layer, where the first bonding pad includes a first copper containing portion, a second semiconductor die containing second semiconductor devices and a second bonding pad that is embedded within a second silicon oxide layer and is bonded to the first bonding pad via metal-to-metal bonding, where the second bonding pad includes a second copper containing portion, and at least one metal silicon oxide layer interposed between the first bonding pad and the second silicon oxide layer. In one embodiment, the at least one metal silicon oxide layer is a manganese silicon oxide layer.

A microelectronic structure with through substrate vias (TSVs) and method for forming the same is disclosed. The microelectronic structure can include a bulk semiconductor with a via structure. The via structure can have a first and second conductive portion. The via structure can also have a barrier layer between the first conductive portion and the bulk semiconductor. The structure can have a second barrier layer between the first and second conductive portions. The second conductive portion can extend from the second barrier layer to the upper surface of the bulk semiconductor. The microelectronic structure containing TSVs is configured so that the microelectronic structure can be bonded to a second element or structure.

A semiconductor package is provided. The semiconductor package includes a first semiconductor substrate, a first semiconductor element layer on an upper surface of the first semiconductor substrate, a first wiring structure on the first semiconductor element layer, a first connecting pad connected to the first wiring structure, a first test pad connected to the first wiring structure, a first front side bonding pad connected to the first connecting pad and including copper (Cu), and a second front side bonding pad connected to the first front side bonding pad and including copper (Cu) which has a nanotwin crystal structure different from a crystal structure of copper (Cu) included in the first front side bonding pad, wherein a width of the first front side bonding pad in the horizontal direction is different from a width of the second front side bonding pad in the horizontal direction.

Some embodiments relate to an integrated device, including: a first interconnect structure on a first substrate; a first central bond pad coupled to the first interconnect structure; a first peripheral bond pad on a first side of the first central bond pad separated by a first distance; a second peripheral bond pad on a second side of the first central bond pad and separated by a second distance substantially equal to the first distance; a second interconnect structure on a second substrate; a first overlying bond pad coupled to the second interconnect structure and bonded to the first central bond pad; and a plurality of exposed bond pads respectively coupled to the first central bond pad, the first peripheral bond pad, the second peripheral bond pad, and the first overlying bond pad, wherein the plurality of exposed bond pads extend past outer sidewalls of the second substrate.

An element, a bonded structure including the element, and a method of forming the same are disclosed. The bonded structure can include a first element having a first nonconductive field region and a first conductive feature at least partially defining a bonding surface of the first element. The first conductive feature includes a first portion and a second portion over the first portion with a continuous sidewall. The second portion includes different metal composition from the first portion or comprising fluorine at the surface of the first conductive feature. A second element has a second nonconductive field region and a second conductive feature which are directly bonded to the first nonconductive field region and a first conductive feature, respectively.