The present disclosure relates to semiconductor devices, and semiconductor devices according to example embodiments include a first substrate structure and a second substrate structure on the first substrate structure, the first substrate structure including a first substrate including a cell area and a scribe lane area surrounding the cell area, first bonding pads over the cell area of the first substrate, and first dummy pads on the first substrate in the scribe lane area, the second substrate structure including a second substrate on the first substrate, and second bonding pads between the first substrate and the second substrate, joined with the plurality of first bonding pads, and a sum of the areas of the first dummy pads per a unit area in the scribe lane area is greater than or equal to a sum of the areas of the first bonding pads per a unit area in the cell area.

A semiconductor package includes a first semiconductor chip including: a first substrate, a first wiring layer on a first surface of the first substrate, a plurality of first dummy pads electrically connected to each other by a redistribution layer disposed between the first wiring layer and a first passivation layer, and a plurality of second dummy pads disposed adjacent to the plurality of first dummy pads on the first wiring layer; and a second semiconductor chip including: a second substrate, a second wiring layer on the second substrate and opposite to the first surface of the first substrate, a plurality of third dummy pads having at least a portion that overlaps the plurality of first dummy pads on the second wiring layer, and a plurality of power pads arranged adjacent to the plurality of third dummy pads and configured to provide a test voltage.

A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semi conductor chip.

An integrated circuit package with a perforated stiffener ring and the method of forming the same are provided. The integrated circuit package may comprise an integrated circuit package component having an integrated circuit die on a substrate, an underfill between the integrated circuit package component and the substrate, and a stiffener ring attached to the substrate. The stiffener ring may encircle the integrated circuit package component and the underfill in a top-down view. The stiffener ring may comprise a perforated region, wherein the perforated region may comprise an array of openings extending from a top surface of the stiffener ring to a bottom surface of the stiffener ring.

A photoelectric conversion apparatus includes a first chip having a first semiconductor element layer including a pixel region of a plurality of pixel circuits, and a second chip having a second semiconductor element layer. The first and second chips are bonded by a plurality of metal bonding portions between the first and second semiconductor element layers. The plurality of metal bonding portions includes first and second metal bonding portions disposed in a region overlapping with the pixel region in a plan view. The first metal bonding portion connects at least either one of the plurality of pixel circuits and the second semiconductor element layer. The second metal bonding portion is connected to at least either one of the plurality of pixel circuits and is not connected to the second semiconductor element layer in the region overlapping with the pixel region.

A semiconductor package according to an embodiment of the present disclosure includes: a substrate; a semiconductor chip on the substrate and electrically connected to the substrate; at least one heat dissipation wire connected to the semiconductor chip; and an encapsulant on at least a portion of each of the semiconductor chip and the heat dissipation wire. The heat dissipation wire is exposed to one side surface of side surfaces of the encapsulant.

A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a device region and a seal ring region surrounding the device region. The semiconductor device structure includes a seal ring structure over the seal ring region. The seal ring structure surrounds the device region. The semiconductor device structure includes a bonding film over the seal ring structure and the substrate. The semiconductor device structure includes a bonding pad embedded in the bonding film. The bonding pad overlaps the seal ring structure along an axis perpendicular to a first top surface of the substrate, and a second top surface of the bonding pad is substantially level with a third top surface of the bonding film.

The present application provides a semiconductor structure having a dummy conductive member, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first wafer including a first substrate, a first dielectric layer over the first substrate, a first bonding layer over the first dielectric layer, a first via extending through the first bonding layer, and a first dummy conductive member disposed adjacent to the first via and extending partially through the first bonding layer; and a second wafer including a second bonding layer over the first bonding layer, a second via extending through the second bonding layer, a second dummy conductive member disposed adjacent to the second via and extending partially through the second bonding layer, a second dielectric layer over the second bonding layer, and a second substrate over the second dielectric layer.

Embodiments of the present disclosure provide a semiconductor structure and a manufacturing method therefor. The structure includes: a first dielectric layer disposed on a substrate, where the first dielectric layer has a first surface away from the substrate; a first bond pad, passing through the first surface and extending to a first depth below the first surface; a second bond pad, passing through the first surface and extending to a second depth below the first surface, where the second depth is less than the first depth; and a second dielectric layer, disposed on the first surface, where a first gap and a second gap are provided in the second dielectric layer, the first gap exposes the top surface of the first bond pad, and the second gap exposes the top surface of the second bond pad.

A semiconductor package includes a semiconductor chip including a semiconductor substrate having an active layer, ground chip pads on the semiconductor substrate, and signal chip pads on the semiconductor substrate and a package substrate supporting the semiconductor chip, the package substrate including a substrate insulating layer, a plurality of signal line patterns extending in the substrate insulating layer and electrically connected to the signal chip pads, and a plurality of ground line patterns extending in the substrate insulating layer at a same level as a level of the plurality of signal line patterns and electrically connected to the ground chip pads. At least one of the plurality of ground line patterns extends between the plurality of signal line patterns.