A field-programmable-gate-array (FPGA) integrated-circuit (IC) chip configured to perform a logic function based on a look-up table (LUT), includes: multiple non-volatile memory cells therein configured to store multiple resulting values of the look-up table (LUT); and a programmable logic block therein having multiple static-random-access-memory (SRAM) cells configured to store the resulting values passed from the non-volatile memory cells, wherein the programmable logic block is configured to select, in accordance with one of the combinations of its inputs, one from the resulting values stored in the static-random-access-memory (SRAM) cells into its output.

A semiconductor device includes a first passivation layer over a substrate. The semiconductor device further includes a post passivation interconnect (PPI) line over the first passivation layer, wherein a top-most portion of the PPI line has a first portion having a convex shape and a second portion having a concave shape. The semiconductor device further includes a second passivation layer configured to cause stress to the PPI line. The semiconductor device further includes a polymer material over the second passivation layer.

Provided are a light-emitting panel and a display device. The light-emitting panel includes a driving substrate and a plurality of light-emitting elements. The driving substrate includes a base substrate, a plurality of driver circuits, and a plurality of photoelectric conversion units. The driver circuits and the photoelectric conversion units are located on the base substrate. A photoelectric conversion unit includes a first doped region and a second doped region. The light-emitting elements are located on a side of the driving substrate. The orthographic projection of a light-emitting element among at least part of the light-emitting elements on the driving substrate is a first projection. An orthographic projection of the photoelectric conversion unit on the driving substrate is located between two adjacent first projections. A driver circuit and the photoelectric conversion unit are each electrically connected to the light-emitting element.

In a general aspect, a semiconductor package includes a first semiconductor die. The semiconductor package includes a second semiconductor die coupled to the first semiconductor die. The semiconductor package includes a plurality of first pillars coupled to the first semiconductor die, each of the first pillars having a first height. The semiconductor package includes a plurality of second pillars coupled to the second semiconductor die, each of the second pillars having a second height that is less than the first height. The semiconductor package includes a mold layer that encapsulates a surface of the first semiconductor die, the second semiconductor die, the plurality of first pillars, and the plurality of second pillars. Top surfaces of the first pillars and top surfaces of the second pillars are exposed at a surface of the mold layer and are substantially coplanar with the surface of the mold layer.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes a die, an underfill layer, a patterned dielectric layer and a plurality of conductive terminals. The die has a front surface and a back surface opposite to the front surface. The underfill layer encapsulates the die, wherein a surface of the underfill layer and the back surface of the die are substantially coplanar to one another. The patterned dielectric layer is disposed on the back surface of the die. The conductive terminals are disposed on and in contact with a surface of the patterned dielectric layer and partially embedded in the patterned dielectric layer to be in contact with the die, wherein a portion of the surface of the patterned dielectric layer that directly under each of the conductive terminals is substantially parallel with the back surface of the die.