A semiconductor package includes a redistribution structure including redistribution patterns, first and second chip structures on the redistribution structure and electrically connected to the redistribution patterns, a first mold covering at least a portion of each of the first and second chip structures, an interconnection chip including interconnection patterns electrically connected to the redistribution patterns and a plurality of insulating layers having third surfaces in which respective ones of the interconnection patterns are embedded, through-vias electrically connected to the redistribution patterns, a second mold covering at least a portion of each of the through-vias and the interconnection chip. Each third surface includes a first region, and a second region between the first region and an upper surface of the respective interconnection pattern embedded in the third surface. The second region defines a step between the first region and the upper surface of the interconnection pattern embedded in the third surface.

A semiconductor package includes a connection substrate on a package substrate and has an opening that penetrates therethrough. A chip stack is on the package substrate and in the opening. A redistribution layer is on the connection substrate and the chip stack. An upper semiconductor chip is on first redistribution pads of the redistribution layer. External terminals are on a bottom surface of the package substrate. The chip stack includes a first semiconductor chip on substrate pads of the package substrate, and a second semiconductor chip on the first semiconductor chip and second redistribution pads of the redistribution layer. The redistribution layer includes a first region that overlaps the upper semiconductor chip and a second region beside the upper semiconductor chip. The first redistribution pads are on the first region. The second redistribution pads are on the second region.

An integration process including an etch stop layer for high density memory and logic applications and methods of fabrication are described. While various examples are described with reference to FeRAM, capacitive structures formed herein can be used for any application where a capacitor is desired. For instance, the capacitive structure can be used for fabricating ferroelectric based or paraelectric based majority gate, minority gate, and/or threshold gate.

A semiconductor package, as a semiconductor package mounted on a circuit board, includes including: a body portion including a semiconductor chip, and a first surface and a second surface opposite to each other; and a structure including n insulating layers stacked on at least one of the first surface and the second surface of the body portion, wherein the semiconductor package has a predetermined target coefficient of thermal expansion (CTE), and the n insulating layers and the body portion have a thickness and a CTE satisfying a condition that an effective CTE of the semiconductor package becomes equal to the predetermined target CTE.

A semiconductor device has a substrate and a first light sensitive material formed over the substrate. A plurality of first conductive posts is formed over the substrate by patterning the first light sensitive material and filling the pattern with a conductive material. A plurality of electrical contacts is formed over the substrate and the conductive posts are formed over the electrical contacts. A first electric component is disposed over the substrate between the first conductive posts. A plurality of second conductive posts is formed over the first electrical component by patterning a second light sensitive material and filling the pattern with conductive material. A first encapsulant is deposited over the first electrical component and conductive posts. A portion of the first encapsulant is removed to expose the first conductive posts. A second electrical component is disposed over the first electrical component and covered with a second encapsulant.

A semiconductor package assembly and an electronic device are provided. The semiconductor package assembly includes a base, a system-on-chip (SOC) package, a memory package and a silicon capacitor die. The base has a first surface and a second surface opposite the first surface. The SOC package is disposed on the first surface of the base and includes a SOC die having pads and a redistribution layer (RDL) structure. The RDL structure is electrically connected to the SOC die by the pads. The memory package is stacked on the SOC package and includes a memory package substrate and a memory die. The memory package substrate has a top surface and a bottom surface. The memory die is electrically connected to the memory package substrate. The silicon capacitor die is disposed on and electrically connected to the second surface of the base.

Embodiments of the invention include molded modules and methods for forming molded modules. According to an embodiment the molded modules may be integrated into an electrical package. Electrical packages according to embodiments of the invention may include a die with a redistribution layer formed on at least one surface. The molded module may be mounted to the die. According to an embodiment, the molded module may include a mold layer and a plurality of components encapsulated within the mold layer. Terminals from each of the components may be substantially coplanar with a surface of the mold layer in order to allow the terminals to be electrically coupled to the redistribution layer on the die. Additional embodiments of the invention may include one or more through mold vias formed in the mold layer to provide power delivery and/or one or more faraday cages around components.

A package structure includes an embedded component circuit structure layer, a signal interconnection structure layer, a power structure layer, and an electronic component layer. The embedded component circuit structure layer includes at least one embedded component and has a first surface and a second surface opposite to each other. The signal interconnection structure layer is disposed on the first surface and is electrically connected to the embedded component circuit structure layer. The power structure layer is disposed on and electrically connected to the signal interconnection structure layer. The electronic component layer includes a plurality of electronic components, is disposed on the second surface, and is electrically connected to the embedded component circuit structure layer. A coefficient of thermal expansion of the signal interconnection structure layer is higher than a coefficient of thermal expansion of the electronic component layer and a coefficient of thermal expansion of the power structure layer.

Disclosed herein is a multi-die device, and an integrated chip package assembly having the multi-die device. The multi-die device includes a first IC die and a second IC die disposed at a same tier; a first conductive pillar coupled with the first IC die; a second conductive pillar coupled with the second IC die; and an interconnecting die disposed between the first conductive pillar and the second conductive pillar and configured to couple with the first IC die and the second IC die. The multi-die device further includes a first interconnecting interface disposed on the first IC die; a second interconnecting interface disposed on the second IC die, the first interconnecting interface and the second interconnecting interface being separated by a molding material.

Embodiments are generally directed to package stacking using chip to wafer bonding. An embodiment of a device includes a first stacked layer including one or more semiconductor dies, components or both, the first stacked layer further including a first dielectric layer, the first stacked layer being thinned to a first thickness; and a second stacked layer of one or more semiconductor dies, components, or both, the second stacked layer further including a second dielectric layer, the second stacked layer being fabricated on the first stacked layer.