A structure including a first semiconductor die, an interposer and a first insulating encapsulation is provided. The first semiconductor die includes a semiconductor substrate, an interconnect structure disposed on the semiconductor substrate and conductive vias disposed on the interconnect structure. The interposer includes a dielectric layer and through vias penetrating through the dielectric layer. The first insulating encapsulation laterally encapsulates the first semiconductor die and the interposer, wherein a thickness of the dielectric layer of the interposer substantially equals to a thickness of the first semiconductor die and a thickness of the first insulating encapsulation.

An electronic device includes a substrate, an outer layer, a conductive line layer, and a switchable circuit chip. The substrate has a plurality of having a plurality of first vias. The outer layer is disposed on a side of the substrate and has a plurality of second vias. The first vias have a larger distribution density or quantity than the second vias, so that a part of the first vias are electrically connected to the second vias, and another part of the first vias are electrically floating. The conductive line layer is disposed on the outer layer and has a plurality of conductive traces. The conductive traces are electrically connected to the second vias. The switchable circuit chip is electrically connected to the first vias. The conductive traces are electrically connected to the switchable circuit chip. The switchable circuit chip is configured for controlling an electrical connecting relationship between the conductive traces and the first vias and an electrical connecting relationship among the conductive traces.

An electronic package structure and manufacturing method thereof. The electronic package structure includes a circuit board, an interposer, a chip, a circuit structure, and a coaxial conductive element. The interposer is disposed on the circuit board. The interposer has a through groove. The chip is disposed in the through groove and located on the circuit board to electrically connect with the circuit board. The circuit structure is disposed on the interposer. The coaxial conductive element penetrates the interposer to electrically connect the circuit structure and the circuit board. The coaxial conductive element includes a first conductive structure, a second conductive structure, and a first insulating structure. The second conductive structure surrounds the first conductive structure. The first insulating structure is disposed between the first conductive structure and the second conductive structure.

A semiconductor package includes: a lower substrate; a semiconductor chip disposed on the lower substrate; an upper substrate disposed on the semiconductor chip, having a lower surface facing the semiconductor chip, and including step structures disposed below the lower surface; a connection structure disposed around the semiconductor chip and connecting the lower substrate to the upper substrate; and an encapsulant filling a space between the lower substrate and the upper substrate and sealing at least a portion of each of the semiconductor chip and the connection structure. The lower surface of the upper substrate has a first surface portion on which the step structures are disposed and a second surface portion having a step with respect to the lower surface of the step structures, and the second surface portion extends between opposite edges of the upper substrate.

Some implementations described herein a provide a multi-die package and methods of formation. The multi-die package includes a dynamic random access memory integrated circuit die over a system-on-chip integrated circuit die, and a heat transfer component between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, which may correspond to a dome-shaped structure, may be on a surface of the system-on-chip integrated circuit die and enveloped by an underfill material between the system-on-chip integrated circuit die and the dynamic random access memory integrated circuit die. The heat transfer component, in combination with the underfill material, may be a portion of a thermal circuit having one or more thermal conductivity properties to quickly spread and transfer heat within the multi-die package so that a temperature of the system-on-chip integrated circuit die satisfies a threshold.

A package structure including a first redistribution layer, a semiconductor die, through insulator vias, an insulating encapsulant and a second redistribution layer. The first redistribution layer includes a dielectric layer, a conductive layer, and connecting portions electrically connected to the conductive layer. The dielectric layer has first and second surfaces, the connecting portions has a first side, a second side, and sidewalls joining the first side to the second side. The first side of the connecting portions is exposed from and coplanar with the first surface of the dielectric layer. The semiconductor die is disposed on the second surface of the dielectric layer. The through insulator vias are connected to the conductive layer. The insulating encapsulant is disposed on the dielectric layer and encapsulating the semiconductor die and the through insulator vias. The second redistribution layer is disposed on the semiconductor die and over the insulating encapsulant.

A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern. The method further includes patterning the photoresist to define a plurality of first openings. The method further includes depositing a conductive material in each of the plurality of first openings. The method further includes disposing a molding material over the first conductive pattern, wherein the molding material surrounds a die. The method further includes removing a portion of the molding material to form a second opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a redistribution structure over the molding material and the dielectric member, wherein the redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

A method includes forming a first dielectric layer, forming a first redistribution line comprising a first via extending into the first dielectric layer, and a first trace over the first dielectric layer, forming a second dielectric layer covering the first redistribution line, and patterning the second dielectric layer to form a via opening. The first redistribution line is revealed through the via opening. The method further includes forming a second via in the second dielectric layer, and a conductive pad over and contacting the second via, and forming a conductive bump over the conductive pad. The conductive pad is larger than the conductive bump, with a first center of conductive pad being offsetting from a second center of the conductive bump. The second via is further offset from the second center of the conductive bump.

An electronic circuit module. The module has a multilayered LTCC circuit carrier made of structured inorganic substrate layers, which have electrical and/or thermal conduction structures for electrical and/or thermal conduction, at least one electronic component, which is arranged on a first side and/or an opposite second side of the LTCC circuit carrier, and at least one SiC power semiconductor. The at least one SiC power semiconductor is embedded in the multilayered LTCC circuit carrier and enclosed at least on three sides by the multilayered LTCC circuit carrier. Connection contacts of the SiC power semiconductor contact the electrical and/or thermal conduction structures of the LTCC circuit carrier.

A high-frequency device includes a metal base, a dielectric substrate mounted on the metal base, an insulator layer provided on the metal base, covering the dielectric substrate, and having a dielectric constant smaller than that of the dielectric substrate, and a first line that overlaps the dielectric substrate as seen from a thickness direction of the insulator layer and is provided on an upper surface of the insulator layer to form a first microstrip line.