A cutting apparatus for dividing a wafer that is stuck to an adhesive tape in which the adhesive layer is cured by ultraviolet light and that is supported by an annular frame through the adhesive tape, into individual chips, includes: a holding unit having a frame support section that supports the annular frame, and a wafer table that is formed of a transparent body and supports the wafer; a cutting unit including, in a rotatable manner, a cutting blade for cutting the wafer; and an ultraviolet light applying unit that applies ultraviolet light, the ultraviolet light applying unit being disposed facing the cutting blade in such a manner that the wafer table is interposed therebetween. The ultraviolet light applying unit applies ultraviolet light to a region where the wafer is to be cut by the cutting blade, to form a cured region where the adhesive layer is cured.

A method includes attaching a carrier to a semiconductor wafer using a release film; removing the carrier from the semiconductor wafer; and performing a treatment process to remove the release film from the semiconductor wafer, the treatment process comprising: flowing an etchant through a diffusion plate within a treatment chamber, the diffusion plate comprising concentric rings separated by dividers, the concentric rings comprising a first concentric ring of holes, a second concentric ring of holes, and a third concentric ring of holes, each of the concentric rings having a different hole density; and performing a cleaning process on the semiconductor wafer.

A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, which each include a single crystal channel; a first metal layer with an overlaying second metal layer; a second level including second transistors, overlaying the first level; a third level including third transistors, overlaying the second level; a fourth level including fourth transistors, overlaying the third level, where the second level includes first memory cells, where each of the first memory cells includes at least one of the second transistors, where the fourth level includes second memory cells, where each of the second memory cells includes at least one of the fourth transistors, where the first level includes memory control circuits, where second memory cells include at least four memory arrays, each of the four memory arrays are independently controlled, and at least one of the second transistors includes a metal gate.

An edge ring used in a chamber comprises a cover with an internal space, a circuit board disposed in the internal space of the cover and at least one electrical element disposed on the circuit board. Here, the electrical element includes a temperature sensor, and temperature of the edge ring, heat distribution generated when ion bombardment occurs in plasma state or heat flux in the edge ring is measured by using the temperature sensor.

A method of forming a semiconductor structure includes forming a photoresist over a first conductive pattern. The method further includes patterning the photoresist to define a plurality of first openings. The method further includes depositing a conductive material in each of the plurality of first openings. The method further includes disposing a molding material over the first conductive pattern, wherein the molding material surrounds a die. The method further includes removing a portion of the molding material to form a second opening. The method further includes disposing a dielectric material into the opening to form a dielectric member. The method further includes forming a redistribution structure over the molding material and the dielectric member, wherein the redistribution structure includes an antenna structure over the dielectric member and electrically connected to the die.

A method for making an electronic package is provided. The method includes providing a substrate strip comprising substrate assemblies, each substrate assembly comprises a first substrate and a second substrate connected to the first substrate via a flexible link, the first substrate comprises a first mounting surface, the second substrate comprises a second mounting surface that is not at a same side of the substrate assembly as the first mounting surface; disposing the substrate strip on a first carrier; attaching a first electronic component onto the first mounting surface; disposing the substrate strip on a second carrier with a plurality of cavities, the first electronic component is received within one of the plurality of cavities; attaching a second electronic component onto the second mounting surface; singulating the substrate assemblies from each other; and bending the flexible link to form an angle between the first substrate and the second substrate.

A back grinding adhesive film used to protect a surface of a wafer, the back grinding adhesive film including a base material layer, and an adhesive resin layer which is formed on one surface side of the base material layer and configured with an ultraviolet curable adhesive resin material, in which, when a viscoelastic characteristic is measured after curing the ultraviolet curable adhesive resin material by irradiating with an ultraviolet ray, a storage elastic modulus at 5 C. E (5 C.) is 2.010.sup.6 to 2.010.sup.9 Pa, and a storage elastic modulus 100 C. E (100 C.) is 1.010.sup.6 to 3.010.sup.7 Pa.

In an embodiment, a device includes: a substrate having a first side and a second side opposite the first side; an interconnect structure adjacent the first side of the substrate; and an integrated circuit device attached to the interconnect structure; a through via extending from the first side of the substrate to the second side of the substrate, the through via being electrically connected to the integrated circuit device; an under bump metallurgy (UBM) adjacent the second side of the substrate and contacting the through via; a conductive bump on the UBM, the conductive bump and the UBM being a continuous conductive material, the conductive bump laterally offset from the through via; and an underfill surrounding the UBM and the conductive bump.

An expansion method includes an expansion step of expanding a sheet between an outer periphery of a wafer and an inner periphery of an annular frame in a wafer unit, and a heating step of heating the sheet in its region between the outer periphery of the wafer and the inner periphery of the annular frame by a heating unit to allow slack of the sheet, the slack having been formed in the expansion step, to shrink. The region includes a first region, and a second region that is harder to shrink by the heating than the first region. On the sheet, heat spots of a temperature higher than that of the sheet surrounding the heat spots are formed with heat radiated to the sheet. In the heating step, the heating unit is moved such that the heat spots are positioned over an entirety of at least the second region.

A semiconductor package includes a first substrate and a first semiconductor device. The first semiconductor device is bonded to the first substrate and includes a second substrate, a plurality of first dies and a second die. The first dies are disposed between the first substrate and the second substrate. The second die is surrounded by the first dies. A cavity is formed among the first dies, the first substrate and the second substrate, and a gap is formed between the second die and the first substrate.