A semiconductor package includes a redistribution structure, a first semiconductor chip above the redistribution structure, a second semiconductor chip on, and offset relative to, the first semiconductor chip, a plurality of first conductive posts extending from a bottom surface of the second semiconductor chip to a top surface of the redistribution structure, a third semiconductor chip on the second semiconductor chip, a plurality of second conductive posts extending from a bottom surface of the third semiconductor chip to the top surface of the redistribution structure, and a molding layer between the top surface of the redistribution structure and the bottom surface of the third semiconductor chip.

A structure includes a first core substrate; an adhesive layer on the first core substrate; a second core substrate on the adhesive layer, wherein the second core substrate includes a first cavity; a first semiconductor device within the first cavity; a first insulating film extending over the second core substrate, over a top surface of the first semiconductor device, and within the first cavity; a through via extending through the first insulating film, the first core substrate, and the second core substrate; a first routing structure on the first core substrate and electrically connected to the through via; and a second routing structure on the first insulating film and electrically connected to the through via and the first semiconductor device.

A microelectronic device is formed to include an embedded die substrate on an interposer; where the embedded die substrate is formed with no more than a single layer of transverse routing traces. In the device, all additional routing may be allocated to the interposer to which the embedded die substrate is attached. The embedded die substrate may be formed with a planarized dielectric formed over an initial metallization layer supporting the embedded die.

A method includes bonding a first plurality of device dies onto a wafer, wherein the wafer includes a second plurality of device dies, with each of the first plurality of device dies bonded to one of the second plurality of device dies. The wafer is then sawed to form a die stack, wherein the die stack includes a first device die from the first plurality of device dies and a second device die from the second plurality of device dies. The method further includes bonding the die stack over a package substrate.

Various embodiments of the teachings herein include a sintered power electronic module with a first plane and a second plane different from the first plane. An example comprises: a first substrate with a first metallization arranged on the first plane; a second substrate with a second metallization arranged on the second plane; a switchable die having a first power terminal and a second power terminal, the die arranged between the first substrate and the second substrate; and a surface area of all the sintered connections of the first plane is between 90 and 110% of a surface area of all the sintered connections of the second plane. The first power terminal of the die is joined to the first metallization via a sintered connection in the first plane and the second power terminal is joined to the second metallization via a sintered connection in the second plane.

A semiconductor package includes a redistribution structure, at least one semiconductor device, a heat dissipation component, and an encapsulating material. The at least one semiconductor device is disposed on and electrically connected to the redistribution structure. The heat dissipation component is disposed on the redistribution structure and includes a concave portion for receiving the at least one semiconductor device and an extending portion connected to the concave portion and contacting the redistribution structure, wherein the concave portion contacts the at least one semiconductor device. The encapsulating material is disposed over the redistribution structure, wherein the encapsulating material fills the concave portion and encapsulates the at least one semiconductor device.

The present disclosure provides a memory system packaging structure and fabrication methods. The memory system packaging structure includes memory modules, a memory controller, a redistribution layer electrically connected to the memory controller, a plastic encapsulation layer encapsulating the memory modules and the memory controller, and one or more connecting pillars extending in the vertical direction and configured for providing electric power to the memory modules. Each memory module includes memory dies stacked in a vertical direction. Each connecting pillar includes a first portion being in physical contact with one of the memory dies and a second portion being in physical contact with the redistribution layer.

Semiconductor packages, and methods for manufacturing semiconductor packages are provided. In one aspect, a method of manufacturing a semiconductor package includes stacking a plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip, the first semiconductor ship being offset from the second semiconductor ship to expose upper connection pads; forming a multilayered photoresist film to cover the plurality of semiconductor chips; forming a plurality of openings by exposing and developing the multilayered photoresist film; forming a plurality of conductive posts by filling the plurality of openings with a conductive material; removing the multilayered photoresist film; forming a molding encapsulant to surround the plurality of semiconductor chips and the plurality of conductive posts; and forming a wiring structure electrically connected to the plurality of conductive posts. The multilayered photoresist film comprises at least two layers having different chemical resistances and resolutions.

A display includes a wiring pad and a dummy pad on a first substrate. A first planarization layer is disposed on the wiring pad and the dummy pad. A first pad electrode layer is connected to the wiring pad and a second pad electrode layer is connected to the dummy pad. The first and second pad electrode layers are disposed on the first planarization layer. A first insulating layer covers the first and second pad electrode layers. A first pad electrode upper layer is disposed on the first pad electrode layer. A second pad electrode upper layer is disposed on the second pad electrode layer. The wiring pad, the first pad electrode layer, and the first pad electrode upper layer are electrically connected. The dummy pad, the second pad electrode layer, and the second pad electrode upper layer are electrically connected.

A device manufacturing method includes: forming a conductive layer, which is to be an air bridge, on a sacrificial layer in a first surface of a chip to pattern form the conductive layer; removing the sacrificial layer other than the sacrificial layer underneath the air bridge; mounting the chip with the sacrificial layer left underneath the air bridge on a board such that the first surface of the chip opposes the board; and removing the sacrificial layer left underneath the air bridge.