A device may include a substrate comprising a plurality of first contact pads disposed on a first surface, and a plurality of second contact pads disposed on a second surface, the substrate comprising a plurality of interconnect structures extending between the first surface and the second surface. A device may include a first portion of an axial extension of the plurality of interconnect structures having sidewalls of a first profile. A device may include a second portion of the axial extension of the plurality of interconnect structures having sidewalls of a second profile, shallower than the first profile.

This disclosure is directed to an interconnect structure of a semiconductor device and a method of forming the interconnect structure. The interconnect structure includes a first metal line, a second metal line on the first metal line, and a conductive via electrically coupling the first and second metal lines. The conductive via includes a protrusion laterally and vertically extending into the first metal line to reduce a contact resistance between the conductive via and the first metal line. The method includes forming the first metal line and a dielectric layer on the first metal line, forming an opening in the dielectric layer to expose the first metal line, and laterally recessing the first metal line in the opening. The method further includes depositing a conductive material in the opening to form the conductive via and the second metal line.

A semiconductor structure with a silicon through via (TSV) includes a semiconductor substrate. A TSV penetrates the semiconductor substrate. The TSV includes a metal layer, a barrier layer and an isolation layer. An end of the metal layer protrudes from a back side of the semiconductor substrate. A recess is disposed at one side of the end of the metal layer. A composite structure fills the recess. The composite structure includes a thermal conductive layer and a first dielectric layer. The thermal conductive layer contacts the sidewall of the end of the metal layer and contacts the barrier layer, the isolation layer and the semiconductor substrate. A first dielectric layer is disposed on the thermal conductive layer. A top surface of the first dielectric layer is aligned with the end of the metal layer. The thermal conductive layer includes aluminum nitride, aluminum oxide or diamond.

A biological sensing system, comprising a microelectrode array having a plurality of islands that are thermally isolated from each other and are interconnected by flexible nano-scale wires. An embedded complementary metal oxide semiconductor (CMOS) instrumentation amplifier and wireless communication circuitry may be operatively connected to the microelectrode array and embedded within input/output pads connected to the wires at the periphery of the array.