In various embodiments, a bonded structure is disclosed. The bonded structure can include an element and a passive electronic component having a first surface bonded to the element and a second surface opposite the first surface. The passive electronic component can comprise a first anode terminal bonded to a corresponding second anode terminal of the element and a first cathode terminal bonded to a corresponding second cathode terminal of the element. The first anode terminal and the first cathode terminal can be disposed on the first surface of the passive electronic component.

A microelectronic device includes a die with input/output (I/O) terminals, and a dielectric layer on the die. The microelectronic device includes electrically conductive pillars which are electrically coupled to the I/O terminals, and extend through the dielectric layer to an exterior of the microelectronic device. Each pillar includes a column electrically coupled to one of the I/O terminals, and a head contacting the column at an opposite end of the column from the I/O terminal. The head extends laterally past the column in at least one lateral direction. Methods of forming the pillars and the dielectric layer are disclosed.

In a semiconductor device, a first structure including a first uneven unit and a second structure covering the first structure and including a second uneven unit are formed in a bonding region defined in a semiconductor substrate. Metal wiring is joined to the second uneven unit in the second structure. A depth of a recess in the second uneven unit is shallower than a depth of a recess in the first uneven unit. An insulating member defining the bonding region is formed so as to reach the semiconductor substrate.

An image pickup unit includes: an image pickup substrate including a first principal surface and a second principal surface, a light receiving circuit being formed on the first principal surface and a through wiring being placed on an inner surface of a via hole including an opening in the second principal surface; a solder resist film placed around the via hole on the second principal surface and in the via hole in a range from a bottom face to a level not reaching the second principal surface; and a bonding terminal which is made of solder, covers a surface of the solder resist film placed in the via hole, and is bonded to the through wiring on an outer edge of the opening in the via hole, the through wiring being not covered with the solder resist film.

A method for depositing copper onto a substrate includes grain engineering to control the internal structure of the copper. In some embodiments, the method comprises depositing a grain control layer conformally onto a copper seed layer in a structure on the substrate where the grain control layer is a non-conducting material, etching the grain control layer using a direct deep reactive ion etch (DRIE) process to remove portions of the grain control layer on horizontal surfaces within the structure, and depositing a copper material onto the structure such that at least one grain parameter of the copper material is controlled, at least in part, by a remaining portion of the grain control layer on vertical surfaces of the structure. In some embodiments, the deposited copper material in the structure has a <111> grain orientation normal to a horizontal surface of the structure.

In a bonding process of a flip chip bonding method, a chip is bonded to contact pads of a substrate by composite bumps which each includes a raiser, a UBM layer and a bonding layer. Before the bonding process, the surface of the bonding layer facing toward the substrate is referred to as a surface to be bonded. During the bonding process, the surface to be bonded is boned to the contact pad and become a bonding surface on the contact pad. The bonding surface has an area greater than that of the surface to be bonded so as to reduce electrical impedance between the chip and the substrate.

The present application provides a semiconductor structure having a conductive pad with a protrusion, and a manufacturing method of the semiconductor structure. The semiconductor structure includes a first die including a first substrate, a first dielectric layer over the first substrate, a first conductive pad at least partially exposed through the first dielectric layer, a first bonding layer over the first dielectric layer, and a first via extending through the first bonding layer and coupled to the first conductive pad; and a second die including a second bonding layer bonded to the first bonding layer, a second substrate over the second bonding layer, and a second via extending through the second substrate and the second bonding layer, wherein a first contact surface area between the first bonding layer and the second via is substantially greater than a second contact surface area between the first via and the second via.

A semiconductor device includes: a first semiconductor structure including a stacked structure of a first dielectric layer and a first bonding dielectric layer; a second semiconductor structure including a stacked structure of a second dielectric layer and a second bonding dielectric layer; and a bonding pad penetrating the stacked structure of the first dielectric layer and the first bonding dielectric layer, and the stacked structure of the second dielectric layer and the second bonding dielectric layer, wherein the first bonding dielectric layer and the second bonding dielectric layer contact each other, and a first width of a first portion of the bonding pad penetrating the first dielectric layer is greater than each of a second width of a second portion of the bonding pad penetrating the first bonding dielectric layer, and a third width of a third portion of the bonding pad penetrating the second bonding dielectric layer.

Barrier or cladding structures that prevent top vias from chemically reacting to tape residue or other impurities address reliability issues in local silicon interposer interconnection in semiconductor packaging by mitigating metal atom migration and wire growth, thereby enhancing long-term reliability. The via cladding structure incorporates a multi-layered barrier comprising, alone or in any combination, SiOCH, SiO.sub.x, SiON, SiN.sub.x, CuO.sub.x, Ta, Ti, TaN, TiN, Mo, MoN, TaC, TiC, TaCN, or TiCN, enhancing electrical performance and long-term reliability. The method of forming the cladding or barrier structure involves a combination of cladding layer deposition, patterning, wet etch, isotropic dry etch or anisotropic dry etch process, flowable dielectric deposition or spin-coat dielectric, and chemical mechanical planarization (CMP) to ensure robust and reliable connections. The integration of these layers mitigates issues related to metal atom migration and wire growth, providing a solution for the growing demand for high-density, high-performance semiconductor packages.

Example embodiments are directed to a semiconductor device including a substrate, a substrate pad placed on the substrate, a substrate insulation layer configured to surround at least a portion of the substrate pad, a passivation layer placed on the substrate insulation layer and a bump pad placed on the passivation layer, electrically connected to the substrate pad and including solder bumps. The bump pad includes a connector recessed toward the substrate, and the connector, when viewed in a first direction perpendicular to a surface of the substrate, includes a shape, in order to reduce or lower a defect occurring in solder bumps when a degree of expansion and contraction varies due to differences in the coefficient of thermal expansion (CTE).