Methods, systems, and devices for bypass interconnections for stacked semiconductor systems are described. An interface between a logic component and a system substrate of a semiconductor system may extend beyond an active area of a memory stack and couple between the logic component and the system substrate via one or more bypass regions. In some examples, through-silicon vias may be formed through portions of a memory stack, such as a semiconductor extension at edges of each memory die, which may be used for transfer of high-speed or high-energy signals. Additionally, or alternatively, a logic component may be placed on top of a stack of memory dies with separate bypass components along one or more sides adjacent to a memory stack, through which bypass interconnects may be formed, allowing for different configurations and avoiding the use of memory component silicon being allocated for such interconnections.

A nonvolatile memory device includes first and second semiconductor layers. The first semiconductor layer includes wordlines extending in a first direction, bitlines extending in a second direction, and a memory cell array connected to the wordlines and the bitlines. The second semiconductor layer is beneath the first semiconductor layer in a third direction, and includes a substrate and an address decoder on the substrate. The address decoder controls the memory cell array, and includes pass transistors connected to the wordlines, and drivers control the pass transistors. In the second semiconductor layer, the drivers are arranged by a first layout pattern along the first and second directions, and the pass transistors are arranged by a second layout pattern along the first and second directions. The first layout pattern is different from the second layout pattern, and the first layout pattern is independent of the second layout pattern.

A method of manufacturing a display device includes forming a thin film transistor layer in an active area of a substrate, forming a metal layer on an edge area of the substrate, transferring first coating patterns to the edge area, the first coating patterns covering a portion of the metal layer corresponding to shapes of side surface lines, etching the metal layer to form the side surface lines, an upper surface of each of the side surface lines being covered by the first coating patterns, transferring a second coating pattern to the edge area, the second coating pattern covering a side surface of each of the side surface lines and the first coating patterns, and transferring light emitting elements to the thin film transistor layer. The second coating pattern includes openings corresponding to the first coating patterns in a plan view.

A semiconductor package may include a first semiconductor chip and a second semiconductor chip on a top surface thereof. The first semiconductor chip may include a first bonding pad on a top surface of a first semiconductor substrate and a first penetration via on a bottom surface of the first bonding pad and penetrating the first semiconductor substrate. The second semiconductor chip may include a second interconnection pattern on a bottom surface of a second semiconductor substrate and a second bonding pad on a bottom surface of the second interconnection pattern and coupled to the second interconnection pattern. The second bonding pad may be directly bonded to the first bonding pad. A width of the first penetration via may be smaller than that of the first bonding pad, and a width of the second interconnection pattern may be larger than that of the second bonding pad.

A semiconductor device includes: a lower semiconductor structure including one or more first lower test pads, one or more second lower test pads that are alternately arranged with the one or more first lower test pads, and a lower test terminal that is electrically connected to the second lower test pad through a second lower test line; and an upper semiconductor structure positioned over the lower semiconductor structure and including an upper test pad and an upper test terminal that is electrically connected to the upper test pad through an upper test line, wherein, when the lower semiconductor structure and the upper semiconductor structure are aligned, the upper test pad overlaps with and contacts a corresponding first lower test pad among the one or more first lower test pads, and is spaced apart from the second lower test pad that is adjacent to the corresponding first lower test pad.

A semiconductor device assembly can include an assembly substrate having a top surface, a top semiconductor device having a bottom surface, and a plurality of intermediary semiconductor devices. Each of intermediary semiconductor device can be bonded to both the assembly substrate top surface and the top device bottom surface. Each intermediary semiconductor device can also include a semiconductor substrate, a memory array, a first bond pad, a second bond pad, and a conductive column. The first bond pad can electrically couple the assembly substrate to the intermediary semiconductor device; the second bond pad can electrically couple the top semiconductor device to the intermediary semiconductor device; and the conductive column can electrically couple the first bond pad to the second bond pad, and can be exclusive of any electrical connection to the memory array.

One aspect of the present disclosure pertains to a method. The method includes receiving a first circuit structure having semiconductor devices, an interconnect structure, first feedthrough vias, top metal lines, redistribution vias, and bond pads. The method includes dicing the first circuit structure to form a top die having a top semiconductor device. The method includes forming a stacked integrated circuit (IC) structure by bonding the top die to a second circuit structure, the second circuit structure having second semiconductor devices, a second interconnect structure, second redistribution vias, and second bond pads. The method includes forming IC top metal lines over the first feedthrough vias, forming an IC passivation layer over the IC top metal lines, forming metal-insulator-metal (MIM) capacitor structures in the IC passivation layer, and forming IC redistribution vias penetrating through the MIM capacitor structures and the IC passivation layer to land on the IC top metal lines.

Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a region of hydrophobic material electrically isolated from any circuitry of the first semiconductor device and configured to have a reduced bonding strength to a facing region relative to the dielectric-dielectric bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

In an embodiment, a device includes: a first integrated circuit die comprising a semiconductor substrate and a first through-substrate via; a gap-fill dielectric around the first integrated circuit die, a surface of the gap-fill dielectric being substantially coplanar with an inactive surface of the semiconductor substrate and with a surface of the first through-substrate via; a dielectric layer on the surface of the gap-fill dielectric and the inactive surface of the semiconductor substrate; a first bond pad extending through the dielectric layer to contact the surface of the first through-substrate via, a width of the first bond pad being less than a width of the first through-substrate via; and a second integrated circuit die comprising a die connector bonded to the first bond pad.

A semiconductor die includes: a main body including a top surface and a bottom surface; a plurality of first bonding pads disposed on the top surface; and a plurality of second bonding pads disposed on the bottom surface. When viewed in a direction perpendicular to the top surface or the bottom surface, the plurality of first bonding pads are disposed at positions that match positions to which the plurality of second bonding pads are shifted in a plane of the bottom surface while maintaining a positional relationship between the plurality of second bonding pads. The main body includes a first inter-die interface circuit and a second inter-die interface circuit. The plurality of first bonding pads are connected to the first inter-die interface circuit, and the plurality of second bonding pads are connected to the second inter-die interface circuit.