A semiconductor structure includes a functional die, a dummy die, a conductive feature, a seal ring and an alignment mark. The dummy die is electrically isolated from the functional die. The conductive feature is electrically connected to the functional die. The seal ring is disposed aside the conductive feature. The alignment mark is disposed between the seal ring and the conductive feature, and the alignment mark is electrically isolated from the dummy die, the conductive feature and the seal ring.

A substrate treatment method includes determining a first model of an upper substrate and a lower substrate based on alignment error data taken by measuring positions of a plurality of alignment marks of each of the upper substrate and the lower substrate, determining a second model of the upper substrate and the lower substrate based on first sampling alignment error data regarding at least one alignment mark from the alignment error data, determining a third model of the upper substrate and the lower substrate based on second sampling alignment error data taken by measuring positions of the at least one alignment mark, determining a fourth model by correcting the third model based on a difference between the second model and the first model, and aligning a position of a substrate selected between the upper substrate and the lower substrate according to the fourth model.

A wafer structure includes a semiconductor substrate including chip regions and a scribe region for separating each of chip regions, an interlayer insulating layer on the first surface of the semiconductor substrate, an upper insulating layer on the interlayer insulating layer, connection structures formed within the chip regions and partially surrounded by the interlayer insulating layer and the upper insulating layer respectively. First to third trenches formed within the scribe region, and extending along a first side of the scribe region and penetrating the upper insulating layer and the interlayer insulating layer, and dummy structures disposed between the first trench and the third trench and between the second trench and the third trench and partially surrounded by the interlayer insulating layer and the upper insulating layer respectively.

Bonded die structures and methods of fabricating bonded die structures with improved stress distribution. A bonded die structure may include a second die bonded to a first die. The sizes, shapes and/or relative position of the first die with respect to the second die may be configured to minimize stress concentrations in the bonded die structure. In some embodiments, a length dimension of a corner region of the second die may be less than a length dimension of the adjacent corner region of the first die, which may aid in redistributing stress away from the corner of the first die. An offset distance between the corner of the second die and the corner of the first die may also be controlled to minimize stress applied to the corner of the first die along a vertical direction. Accordingly, crack formation may be reduced, and device performance and yields may be improved.

A bonding apparatus includes a first holder, a second holder, a mover, an optical system, an adjusting device and control circuitry. The first holder holds a first substrate. The second holder holds a second substrate. The mover brings a first one of the first holder and the second holder closer to a second one of the first holder and the second holder. The optical system images alignment marks provided on the first substrate and the second substrate. The adjusting device adjusts a depth of focus of the optical system. The control circuitry performs an approach processing and an imaging processing. In the approach processing, the control circuitry brings the first one closer to the second one. In the imaging processing, the control circuitry images, during the approach processing, the alignment marks, after locating the first substrate and the second substrate within the depth of focus of the optical system.

A film formation method of forming a planarized film on a substrate, includes bringing a circular region of a mold, in which the planarized film should be formed, into contact with a composition on the substrate, performing alignment between the substrate and the mold in a state in which the composition and the mold are in contact, and applying curing energy to the composition after the performing alignment, wherein after a part of the mold contacts the composition in the bringing the mold into contact with the composition, the performing alignment is started before an entire surface of the circular region of the mold contacts the composition.

A structure including stacked substrates, a first semiconductor die, a second semiconductor die, and an insulating encapsulation is provided. The first semiconductor die is disposed over the stacked substrates. The second semiconductor die is stacked over the first semiconductor die. The insulating encapsulation includes a first encapsulation portion encapsulating the first semiconductor die and a second encapsulation portion encapsulating the second semiconductor die.

A semiconductor device assembly including a first semiconductor wafer having a first side and a second side opposite the first side, the first semiconductor wafer including: a first plurality of semiconductor devices at the first side, a plurality of non-metallic vias extending from the second side towards the first side, and a plurality of alignment marks, each vertically aligned with a corresponding one or more of the plurality of non-metallic vias, a second semiconductor wafer including a second plurality of semiconductor devices and a plurality of registration marks, each of the plurality of registration marks vertically aligned with a corresponding one or more of the plurality of alignment marks.

Provided is a semiconductor device manufacturing method including a process of annealing a semiconductor wafer in a state in which a supported portion on a lower surface of the semiconductor wafer is supported by using a supporting portion, wherein the supported portion includes one or a plurality of supporting portions and the supporting portion includes one or a plurality of supporting portions, the method comprising: forming impurity regions including a first impurity in a region which is overlapped with the supported portion in a top view and which is apart from an edge of the semiconductor wafer; annealing the semiconductor wafer in a state in which the lower surface of the semiconductor wafer is supported by the supporting portion; and removing the impurity regions by removing a region including the lower surface of the semiconductor wafer.

Provided is a method of controlling a semiconductor process including obtaining measurement data by measuring an alignment mark of a wafer based on multiwavelength light emitted by a plurality of semiconductor process apparatuses, and obtaining a final position of the alignment mark by applying a current weight to the measurement data, measuring overlays of a plurality of measurement positions of the wafer by applying the current weight, generating overlay data by adding the measured overlays, obtaining first indices based on the measurement data and the overlay data and obtaining second indices based on the overlay data, determining at least one weight as a weight candidate group based on the first indices corresponding to each of the plurality of semiconductor process apparatuses, determining a weight from the weight candidate group as a final weight, and modifying the current weight to the final weight.