A semiconductor device includes a substrate including an overlay key region and a plurality of key patterns on the overlay key region. The plurality of key patterns include first to seventh key patterns. The second to seventh key patterns are arranged to enclose the first key pattern in a clockwise direction and to have center points forming a hexagonal shape.

A method for manufacturing a semiconductor device includes forming an insulating film on a substrate; forming a recess portion extending toward the substrate from an upper surface of the insulating film; forming a first film on the upper surface of the insulating film and along an inner surface of the recess portion, wherein the first film has hydrophobicity; treating an upper surface of the first film to be hydrophilic; and polishing the first film until the upper surface of the insulating film is exposed.

An electronic device comprising a multideck structure including a base stack of materials and one or more stacks of materials on the base stack of materials, at least one high aspect ratio feature in an array region in the base stack of materials and in the one or more stacks of materials, and overlay marks including an optical contrast material in or on only an upper portion of the base stack of materials in an overlay mark region of the electronic device is disclosed. The overlay mark region is laterally adjacent to the array region and the overlay marks are adjacent to at least one additional high aspect ratio feature in the base stack of materials. Additional electronic devices and memory devices are disclosed.

A semiconductor package includes a first semiconductor chip, a plurality of second semiconductor chips stacked on the first semiconductor chip, and having widths narrower than a width of the first semiconductor chip, and a molded layer on an upper surface of the first semiconductor chip. The first semiconductor chip includes first front-surface pads, a first back-surface insulating layer divided into a first region and a second region, first back-surface pads in the first region, dummy pads in the second region, the dummy pads respectively having an upper surface on which a metal oxide film is disposed, and a first through-electrode electrically connecting the first front-surface pads and the first back-surface pads to each other. The plurality of second semiconductor chips respectively includes second front-surface pads, second back-surface pads, and a second through-electrode electrically connecting the second front-surface pads and the second back-surface pads to each other.

A semiconductor device includes a substrate having first and second regions; a first stack structure including lower gate electrodes stacked in a first direction in the first region; a first channel structure penetrating through the first stack structure; a second stack structure on the first stack structure and the first channel structure and including upper gate electrodes stacked in the first direction; a second channel structure penetrating through the second stack structure; a first mold structure including lower horizontal sacrificial layers stacked in the second region; an alignment structure penetrating through the first mold structure; and a second mold structure on the first mold structure and the alignment structure and including upper horizontal sacrificial layers stacked, wherein the number of the lower horizontal sacrificial layers is less than the number of the lower gate electrodes.

A method of forming a self-aligned waveguide is provided. The method includes forming a first alignment feature on a packaged semiconductor device and a second alignment feature on a waveguide structure. A solder material is applied to the first alignment feature or the second alignment feature. The waveguide structure is placed onto the packaged semiconductor device such that the second alignment feature overlaps the first alignment feature. The solder material is reflowed to cause the waveguide structure to align with the packaged semiconductor device.

Embodiments of bonded semiconductor structures and fabrication methods thereof are disclosed. In an example, a bonded structure includes a first bonding layer including a first bonding contact and a first bonding alignment mark, a second bonding layer including a second bonding contact and a second bonding alignment mark, and a bonding interface between the first bonding layer and the second bonding layer. The first bonding alignment mark is aligned with the second bonding alignment mark at the bonding interface, such that the first bonding contact is aligned with the second bonding contact at the bonding interface. The first bonding alignment mark includes a plurality of first repetitive patterns. The second bonding alignment mark includes a plurality of second repetitive patterns different from the plurality of first repetitive patterns.

An electronic device includes a first insulating layer and a first connective portion at least partially disposed in the first insulating layer. The electronic device includes a first conductive portion and a second conductive portion. The first conductive portion and the second conductive portion are respectively corresponding to opposite sides of the first insulating layer. The first conductive portion is electrically connected to the second conductive portion through the first connective portion. The electronic device also includes an integrated circuit and a capacitor. The integrated circuit and the capacitor are respectively corresponding to opposite sides of the first insulating layer. The integrated circuit and the capacitor are overlapped with the first connective portion.

There is provided a semiconductor device capable of improving element performance and the degree of integration of elements by forming an alignment mark that may prevent misalignment in a photo process. The semiconductor device includes a base film, a plurality of lower alignment insulating patterns disposed on the base film, and an upper alignment insulating pattern disposed on the lower alignment insulating patterns, extending in a first direction, and in direct contact with each of the lower alignment insulating patterns, wherein the lower alignment insulating patterns extend in a second direction perpendicular to the first direction and are spaced apart from each other in the first direction.

Disclosed are an alignment mark used for aligning a first semiconductor wafer and a second semiconductor wafer in a wafer bonding process in which the first semiconductor wafer and a flipped second semiconductor wafer are aligned and bonded such that the surfaces on which semiconductor elements are formed face each other, and to a wafer bonding method using the same. The alignment mark includes a first alignment mark formed in a predetermined region of the first semiconductor wafer and having a first center of symmetry and a second alignment mark formed in a predetermined region of the second semiconductor wafer and having a second center of symmetry, the second alignment mark being configured to overlap the first alignment mark in a flipped state when the first semiconductor wafer and the flipped second semiconductor wafer are bonded.