The present disclosure provides a semiconductor structure, a method of manufacturing the semiconductor structure and a system for manufacturing the semiconductor structure. The method includes several operations. A substrate including a device region and a scribe line region is provided. A first layer is formed over the substrate. A first photoluminescent layer is formed over the first layer in the scribe line region. The first layer and the first photoluminescent layer are patterned to form a first pattern in the scribe line region. A first patterned mask layer is formed over a second layer. An alignment of the first patterned mask layer with the first pattern is detected. A pattern of the first patterned mask layer is transferred to the second layer to form a second pattern in the scribe line region.

A semiconductor device includes a first-tier structure and a second-tier structure. The first-tier structure includes a silicon portion with through-vias formed through the silicon portion after a back end of line process. The first-tier structure is attached to a first carrier that includes an alignment mark used to form the through-vias and the corresponding backside bump pad metal that are aligned with the through-vias at locations based on the alignment mark. The second-tier structure is bonded to the first-tier structure with the backside bump pad metals interposed between the two tiers. In some embodiments, the through-vias are a reverse pillar shape with a bottom recess and a specified ratio between a top portion and bottom portion.

A semiconductor device includes a substrate that comprises a first region and a second region; a first wiring structure on the first region of the substrate, wherein the first wiring structure comprises a lower bonding pad; a second wiring structure on the first wiring structure, wherein the second wiring structure comprises an upper bonding pad that contacts the lower bonding pad; a lower alignment pattern on the second region of the substrate, wherein the lower alignment pattern is spaced apart from the lower bonding pad; and an upper alignment pattern on the second region of the substrate, wherein the upper alignment pattern is spaced apart from the upper bonding pad, wherein the lower alignment pattern comprises sub-lower alignment patterns, and wherein the upper alignment pattern comprises sub-upper alignment patterns.

Aspects of the present invention provide a semiconductor structure. The semiconductor structure may include a substrate having a first substrate alignment structure. The semiconductor structure may also include a first die with a first die alignment structure. The first die may be attached to the substrate with the first substrate alignment structure matched to the first die alignment structure.

A non-volatile memory device and a non-volatile memory system comprising the same are provided. The non-volatile memory device includes a first stack in which a first conductive pattern and a first dielectric layer are alternately stacked in a first direction on a substrate, a second stack in which a second conductive pattern and a second dielectric layer are alternately stacked in the first direction on the first stack opposite the substrate, a first monitoring channel structure that penetrates the first stack in the first direction, and a second monitoring channel structure that penetrates the second stack in the first direction and is on the first monitoring channel structure. A width of a top of the first monitoring channel structure opposite the substrate is smaller than a width of a bottom of the second monitoring channel structure adjacent the top of the first monitoring channel structure.

The disclosed technology relates to methods for producing an interconnect structure on the back side of an integrated circuit chip. According to a first aspect, a via opening is etched in a top semiconductor layer, and filled with a sacrificial material, thereby forming a sacrificial pillar. Then front and back end of line portions are processed and the substrate is thinned. The etch stop layer and the sacrificial pillar are removed, and replaced an electrically conductive material forming a through semiconductor via. According to a second aspect, the sacrificial pillar is etched through the opening of a trench that intersects the pillar. Filling the trench with a conductive material also fills the cavity created by etching back the pillar resulting in an integral conductive pad and interconnect rail structure. The pillar can be removed and replaced by a conductive material, thereby creating the TSV connection.

A stacking structure including a first bonding structure, a first die and a second die is provided. The first die is disposed on a first side of the first bonding structure, and the first die includes a second bonding structure. A first encapsulation material wraps around the first die. The second die is disposed on a second side of the first bonding structure opposite to the first side, and the second die includes a third bonding structure and through die vias. A second encapsulation material wraps around the second die. The second bonding structure of the first die is bonded with the first bonding structure, and the third bonding structure of the second die is bonded with the first bonding structure located between the first and second dies and the first and second encapsulation materials.

Composite IC die structures comprising a first IC die that has a first region directly bonded to a second IC die across a hybrid-bond interface and a topographic feature extending from a second region of the first IC die. In some examples, a hybrid bond interface is fabricated prior to forming a topographic IC die feature. In other examples, a hybrid bond interface is fabricated after forming a topographic IC die feature. A PIC die comprising a planar optical waveguide further includes an optical coupler protruding from a region of the die. In another region of the PIC die metallization features are embedded with a dielectric material suitable for forming a hybrid bond with a surface of an EIC die. Scaling of the directly bonded interconnections between the PIC and EIC die may facilitate further disintegration of the optical and electrical domains within a heterogenous chip/chiplet assembly.

The semiconductor package includes a semiconductor chip; a first bonding layer including a first inner bonding layer and a first outer bonding layer sequentially stacked on the semiconductor chip along a vertical direction; first inner bonding pads accommodated in the first inner bonding layer on the bonding region of the substrate, and first inner align key patterns accommodated in the first inner bonding layer on the align key region of the substrate; first outer bonding pads accommodated in the first outer bonding layer on the bonding region of the substrate and first outer align key patterns accommodated in the first outer bonding layer on the bonding region of the substrate; a second bonding layer including a second outer bonding layer and a second inner bonding layer sequentially stacked on the first bonding layer along the vertical direction; and a second semiconductor chip disposed on the second bonding layer.

A method of inspecting the substrate according to an embodiment of the present disclosure may include placing a substrate including a plurality of cells, a first alignment key, and a second alignment key spaced apart from the first alignment key in a plan view on a stage, performing a first correcting which corrects misalignment of a first camera using the first alignment key, obtaining a first image by capturing an image of the substrate with the first camera, detecting a foreign substance in the first image, moving the stage such that the substrate overlaps a second camera in a plan view, performing a second correcting which corrects misalignment of the second camera using the second alignment key, and obtaining a second image by capturing, with the second camera, an image of a cell among the cells in which the foreign substance is detected.