A semiconductor package includes: a first semiconductor chip; a second semiconductor chip stacked on the first semiconductor chip to form a stepped shape in a first direction; a first alignment key on the first semiconductor chip, the first alignment key having a first surface parallel to the first direction and a second surface parallel to a second direction perpendicular to the first direction; and a second alignment key on the second semiconductor chip, the second alignment key having a third surface parallel to the first direction and a fourth surface parallel to the second direction, wherein a surface of the second semiconductor chip, which is parallel to the second direction, is aligned with the second surface of the first alignment key in the first direction, and wherein the first surface of the first alignment key is aligned with the third surface of the second alignment key in the second direction.

Semiconductor devices and a method for manufacturing the semiconductor devices are provided. The method includes forming a plurality of bit-line structures on a chip region of a substrate, forming a first alignment key pattern on a scribe line region of the substrate, forming a first alignment key trench in at least a portion of the first alignment key pattern, forming a landing pad layer between the plurality of bit-line structures and on top surfaces of the plurality of bit-line structures, forming a gap-fill layer on the landing pad layer and in an unoccupied portion of the first alignment key trench and performing a planarization process on the gap-fill layer and the landing pad layer.

A method for manufacturing a semiconductor package includes forming a first semiconductor chip having a first bonding surface, the first semiconductor chip including a first outermost insulating layer providing the first bonding surface, a first internal insulating layer on the first outermost insulating layer, a first external marks within the first outermost insulating layer, and a first internal mark within the first internal insulating layer. The first external marks include a first pattern having a first center portion and a second pattern having a first ring portion surrounding the first center portion when viewed in a plan view, the first internal mark is disposed between the first center portion and the first ring portion when viewed in the plan view, and the first external marks and the first internal mark together form a first alignment structure.

A luminous panel includes a circuit board, a plurality of connecting pads, a chip and two alignment structures. The connecting pads are located on the circuit board. The chip is located on the circuit board and at least partially covers the connecting pads. The two alignment structures are located on the circuit board. The two alignment structures and the connecting pads are at the same level. The two alignment structures are located at two diagonal corners of the chip. At least one part of the two alignment structures protrudes from the outline of the chip.

An embodiment semiconductor device includes an interposer, a semiconductor die electrically connected to the interposer, an integrated passive device die electrically connected to the interposer, the integrated passive device die including two or more seal rings, and a first alignment mark formed on the integrated passive device die within a first area enclosed by a first one of the two or more seal rings. The integrated passive device die may further include two or more integrated passive devices located within respective areas enclosed by respective ones of the two or more seal rings. Each of the two or more integrated passive devices may include electrical connections that are formed as a plurality of micro-bumps, and the first alignment mark may be electrically isolated from the electrical connections, and the first alignment mark and the electrical connections may share a common material.

Provided is a semiconductor device for manufacturing a 3D NAND flash memory with high capacity and high performance. The semiconductor device includes: a first device structure layer on a substrate; an interconnect structure layer on the first device structure layer, which includes first pads at a surface thereof; a second device structure layer on the interconnect structure layer, which includes second pads at a surface thereof; a pattern structure at an interface between the interconnect structure layer and the second device structure layer; a first seal ring at the surface of the interconnect structure layer, which surrounds the pattern structure; a second seal ring at the surface of the second device structure layer, which surrounds the pattern structure. The first pad is connected to the second pad, and the first seal ring is connected to the second seal ring.

A method for manufacturing a semiconductor device, including: providing a substrate including an element region and a scribe lane region; forming a first mask pattern on the element region of the substrate, and a spacer on a side face of the first mask pattern; forming a mask film that extends along the first mask pattern, the spacer, and the substrate, wherein the mask film includes a stepped portion on the scribe lane region of the substrate; forming a sacrificial pattern filling the stepped portion; forming a second mask pattern by etching the mask film to expose the first mask pattern and the spacer; removing the spacer and the sacrificial pattern; and forming a gate trench inside the substrate using the first mask pattern and the second mask pattern as etching masks

A semiconductor package including: a first semiconductor chip; and a second semiconductor chip on the first semiconductor chip, wherein the first semiconductor chip includes: a first substrate, a first semiconductor device provided on a first surface of the first substrate, a first interconnection layer on the first surface of the first substrate, an insulating layer covering a second surface of the first substrate that is opposite to the first surface of the first substrate, a first via and a second via penetrating the first substrate and the insulating layer in a first direction that is perpendicular to the first surface of the first substrate, and a connection pattern on a surface of the insulating layer and connected to the first via and the second via, wherein a surface of the first via is coplanar with the surface of the insulating layer.

To improve performance of a semiconductor device. A semiconductor device includes a wiring substrate, a semiconductor chip mounted on a first upper surface of the wiring substrate, an electronic component mounted on the first upper surface, and a stiffener ring fixed to the first upper surface. The stiffener ring includes a first portion arranged to continuously surround a periphery of the semiconductor chip in plan view and adhering to the first upper surface of the wiring substrate, and a second portion connected to the first portion and arranged at a position spaced away from the first upper surface of the wiring substrate in plan view. The second portion of the stiffener ring partially overlaps the electronic component.

A semiconductor structure includes a first layer, a second layer, and a third layer bonded together in a multi-layer stack. The first layer includes a first alignment section, the second layer includes a second alignment section, and the third layer includes a third alignment section and a fourth alignment section. The third alignment section is along a first X-ray path with the first alignment section and the fourth alignment section is along a second X-ray path with the second alignment section.