A semiconductor device includes a transistor layer including a semiconductor substrate and gate structures on an upper surface of the semiconductor substrate, an upper substrate on the transistor layer, an upper wiring layer disposed between the transistor layer and the upper substrate and including upper conductive lines, a bonding layer between the upper wiring layer and the upper substrate, and a lower wiring layer disposed on a lower surface of the semiconductor substrate and including lower conductive lines. The transistor layer is disposed between the lower wiring layer and the upper wiring layer. The bonding layer includes a material having higher thermal conductivity than silicon oxide, and a dopant concentration of the upper substrate is lower than a dopant concentration of the semiconductor substrate.

An electronic package is provided, where a laterally diffused metal oxide semiconductor (LDMOS) type electronic structure is mounted onto a complementary metal oxide semiconductor (CMOS) type electronic element to be integrated into a chip module, thereby shortening electrical transmission path between the electronic structure and the electronic element so as to reduce the communication time between the electronic structure and the electronic element.

Semiconductor devices and methods of manufacturing are provided, wherein a first passivation layer is deposited over a top redistribution structure; a second passivation layer is deposited over the first passivation layer; and a first opening is formed through the second passivation layer. After the forming the first opening, the first opening is reshaped into a second opening; a third opening is formed through the first passivation layer; and filling the second opening and the third opening with a conductive material.

A three-dimensional (3D) integrated circuit (IC) (3DIC) package with a bottom die layer employing an interposer substrate, and related fabrication methods. To facilitate the ability to fabricate the 3DIC package using a top die-to-bottom wafer process, a bottom die layer of the 3DIC package includes an interposer substrate. This interposer substrate provides support for a bottom die(s) of the 3DIC package. The interposer substrate is extended in length to be longer in length than the top die. The interposer substrate provides additional die area in the bottom die layer in which a larger length, top die can be bonded. In this manner, the bottom die layer, with its extended interposer substrate, can be formed in a bottom wafer in which the top die can be bonded in a top die-to-bottom wafer fabrication process.

A semiconductor device including a redistribution substrate and a semiconductor chip on the redistribution substrate. The redistribution substrate includes an under-bump pad on a bottom surface of the redistribution substrate. The under-bump pad comprises a first pad part, a second pad part on the first pad part, and a via part that protrudes from the second pad part and contacts the first pad part. The first pad part has a first width in a first direction parallel to a top surface of the redistribution substrate. The second pad part has a second width in the first direction. The second width is greater than the first width.

An offset interposer includes a land side including land-side ball-grid array (BGA) and a package-on-package (POP) side including a POP-side BGA. The land-side BGA includes two adjacent, spaced-apart land-side pads, and the POP-side BGA includes two adjacent, spaced-apart POP-side pads that are coupled to the respective two land-side BGA pads through the offset interposer. The land-side BGA is configured to interface with a first-level interconnect. The POP-side BGA is configured to interface with a POP substrate. Each of the two land-side pads has a different footprint than the respective two POP-side pads.

A chip package structure is provided. The chip package structure includes a substrate. The chip package structure includes a chip over the substrate. The chip package structure includes a first heat conductive layer between the heat-spreading wall structure and the chip. The chip package structure includes a second heat conductive layer over the chip and surrounded by the first heat conductive layer. The chip package structure includes a heat-spreading lid over the substrate and covering the heat-spreading wall structure, the first heat conductive layer, the second heat conductive layer, and the chip. The heat-spreading lid is bonded to the substrate, the heat-spreading wall structure, the first heat conductive layer, and the second heat conductive layer.

An electronic device package includes a circuit layer, a first semiconductor die, a second semiconductor die, a plurality of first conductive structures and a second conductive structure. The first semiconductor die is disposed on the circuit layer. The second semiconductor die is disposed on the first semiconductor die, and has an active surface toward the circuit layer. The first conductive structures are disposed between a first region of the second semiconductor die and the first semiconductor die, and electrically connecting the first semiconductor die to the second semiconductor die. The second conductive structure is disposed between a second region of the second semiconductor die and the circuit layer, and electrically connecting the circuit layer to the second semiconductor die.

A semiconductor device includes one and the other wiring groups that are arranged at an interval in a first direction X, the one and the other wiring groups each including first lower wirings and second lower wirings arrayed as stripes extending in the first direction X, a first pad wiring that is arranged over the one and the other wiring groups and is electrically connected to at least one of the first lower wirings of each of the wiring groups, and a second pad wiring that is arranged over the one and the other wiring groups at an interval from the first pad wiring in a second direction Y intersecting the first direction X and is electrically connected to at least one of the second lower wirings of each of the wiring groups.

A die includes a substrate, a conductive pad, a connector a protection layer, and a passivation layer. The conductive pad is disposed over the substrate. The connector is disposed on the conductive pad. The connector comprises a seed layer and a conductive post on the seed layer. The protection layer laterally covers the connector. The passivation layer is disposed between the protection layer and the conductive pad. The conductive post is separated from the passivation layer and the protection layer by the seed layer.