Patent classifications
H
H10
H10W
72/00
H10W72/244
SEMICONDUCTOR DEVICE AND METHOD
20260144122
·
2026-05-21
·
A method includes forming a passivation structure over a first conductive feature; forming an opening in the passivation structure to expose the first conductive feature; forming a protection layer over the passivation structure and within the opening, wherein the protection layer over the passivation structure has a first thickness; recessing a portion of the protection layer to form a recess, wherein the recess exposes the first conductive feature, wherein a second thickness of the protection layer at a sidewall of the recess is smaller than the first thickness; and forming a second conductive feature over the protection layer and within the recess.