Patent classifications
H10W40/259
INTEGRATED CIRCUIT PACKAGE CAPABLE OF INDEPENDENTLY ASSEMBLING PASSIVE DEVICE AND MANUFACTURING METHOD THEREOF
The present invention provides an integrated circuit package capable of independently assembling passive devices and a manufacturing method thereof. The integrated circuit package includes: an integrated circuit configured to be mounted on a circuit board; and a heat dissipation structure, which is manufactured independently and has a first-layer flat plate disposed above the integrated circuit and in thermal contact therewith, and a cavity located on one side of the first-layer flat plate. The cavity is formed with at least one opening to accommodate a passive device. During assembly, the passive device is inserted into the cavity of the heat dissipation structure through the at least one opening and is electrically connected to the circuit board or the integrated circuit via an electrical conductor of the passive device. Heat generated by the integrated circuit is transferred through the heat dissipation structure.
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING SEMICONDUCTOR PACKAGE
A semiconductor package includes a substrate, a device die, an encapsulating material, a thermal conductive layer, a filling material, and a carrier. The device die is disposed over the substrate. The encapsulating material is disposed over the substrate and laterally encapsulates the device die. The thermal conductive layer conformally covers the device die and the encapsulating material, wherein a profile of the thermal conductive layer comprises a valley portion. The filling material is disposed over the thermal conductive layer and fills the valley portion, wherein a thermal conductivity of the thermal conductive layer is higher than a thermal conductivity of the filling material. The carrier is bonded to the thermal conductive layer and the filling material.
Permanent layer for bump chip attach
Disclosed herein are microelectronics package architectures utilizing glass layers and methods of manufacturing the same. The microelectronics packages may include a silicon layer, dies, and a glass layer. The silicon layer may include vias. The dies may be in electrical communication with vias. The glass layer may include interconnects in electrical communication with the vias.
PACKAGE STRUCTURE
A package structure includes a substrate, an electronic device and a heat dissipating structure. The electronic device is disposed over the substrate. The heat dissipating structure is disposed over the substrate and is attached to the electronic device. The heat dissipating structure includes a heat dissipating portion and a conductive portion. The heat dissipating portion is configured to guide a heat generated by the electronic device to an outside of the package structure. The conductive portion is electrically connected to the substrate, and extends through the heat dissipating portion
SEMICONDUCTOR PACKAGE
A semiconductor package includes a package substrate, a semiconductor chip on an upper surface of the package substrate, the semiconductor chip having a first surface facing the package substrate and a second surface opposite to the first surface, the semiconductor chip having a first thermal expansion coefficient, a stress control layer on the second surface of the semiconductor chip, the stress control layer having a second thermal expansion coefficient greater than the first thermal expansion coefficient so as to have a residual stress in a compressive direction, and a sealing member on the upper surface of the package substrate and covering the semiconductor chip and the stress control layer.
SEMICONDUCTOR DEVICE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
A semiconductor device including a through-via having an improved heat dissipation characteristic and a semiconductor package including the semiconductor device are provided. The semiconductor device includes a semiconductor substrate, an active layer on a lower surface of the semiconductor substrate, a through-via passing through the semiconductor substrate and extending, and a heat dissipation layer including an aluminum nitride (AlN) layer and disposed on an upper surface of the semiconductor substrate to surround a side surface of an upper portion of the through-via.