A method of forming a semiconductor device comprises the following steps. A dielectric layer is formed over a substrate. Source/drain contact layers are formed in the dielectric layer. A 2D material layer is formed over the dielectric layer and the source/drain contact layers. An annealing process is performed to the 2D material layer. After performing the annealing process, a tellurization process is performed to the 2D material layer. A gate structure is formed over the 2D material layer.

A method for controlling a concentration of donors in an Al-alloyed gallium oxide crystal structure includes implanting a Group IV element as a donor impurity into the crystal structure with an ion implantation process and annealing the implanted crystal structure to activate the Group IV element to form an electrically conductive region. The method may further include depositing one or more electrically conductive materials on at least a portion of the implanted crystal structure to form an ohmic contact. Examples of semiconductor devices are also disclosed and include a layer of an Al-alloyed gallium oxide crystal structure, at least one region including the crystal structure implanted with a Group IV element as a donor impurity with an ion implantation process and annealed to activate the Group IV element, an ohmic contact including one or more electrically conductive materials deposited on the at least one region.

A transistor may be provided by forming, in a forward order or in a reverse order, a gate electrode, a semiconducting metal oxide liner, a gate dielectric, and an active layer over a substrate, and by forming a source electrode and a drain electrode on end portions of the active layer. The semiconducting metal oxide liner comprises a thin semiconducting metal oxide material that functions as a hydrogen barrier material.

Embodiments of present invention provide a semiconductor structure. The semiconductor structure includes a first and a second nanosheet (NS) transistor on top of a semiconductor substrate; a shared source/drain (S/D) contact surrounding a first S/D region of the first NS transistor and a second S/D region of the second NS transistor; and a gate-cut structure isolating a first metal gate of the first NS transistor from a second metal gate of the second NS transistor, where a portion of the gate-cut structure is surrounded by the shared S/D contact at a top and sidewalls of the gate-cut structure. A method of forming the same is also provided.

A semiconductor device with a small variation in transistor characteristics is provided. The semiconductor device includes an oxide semiconductor film, a source electrode and a drain electrode over the oxide semiconductor film, an interlayer insulating film placed to cover the oxide semiconductor film, the source electrode, and the drain electrode, a first gate insulating film over the oxide semiconductor film, a second gate insulating film over the first gate insulating film, and a gate electrode over the second gate insulating film. The interlayer insulating film has an opening overlapping with a region between the source electrode and the drain electrode, the first gate insulating film, the second gate insulating film, and the gate electrode are placed in the opening of the interlayer insulating film, the first gate insulating film includes oxygen and aluminum, and the first gate insulating film includes a region thinner that is than the second gate insulating film.

A transistor structure (e.g., a backend transistor structure in an interconnect layer of a semiconductor device) is formed to include an oxide-semiconductor channel layer having a high electron concentration oxide-semiconductor material. The high electron concentration oxide-semiconductor material enables a low threshold voltage and a low channel resistance to be achieved for the oxide-semiconductor channel layer, which enables a high on current to be achieved for the transistor structure. To provide channel control over the oxide-semiconductor channel layer, an oxide-semiconductor barrier layer is included between the source/drain electrodes of the transistor structure and the oxide-semiconductor channel layer. The oxide-semiconductor barrier layer includes a low electron concentration oxide-semiconductor material, which enables increased control over the conductivity of the oxide-semiconductor channel layer to be achieved, which enables a low off current leakage to be achieved for the transistor structure.

The present invention relates to a method for manufacturing multi-pixel gas microsensors, wherein each multi-pixel gas microsensor comprises at least a first pixel group having a first sensing material and a second pixel group having a second sensing material different from the first material. The method comprises a first step of providing a wafer substrate and processing the wafer substrate for building a plurality of multi-pixel microsensors having first and second groups of pixels, a second step of selecting sensing materials for each of the groups of pixels, and a third step of activation of the first and the second pixel group by coating electrode pairs of the first and second pixel group with the corresponding sensing materials selected.

A method of fabricating a semiconductor device includes forming a semiconductor layer, the semiconductor layer including a two-dimensional semiconductor material, forming a sacrificial layer on the semiconductor layer, forming a metal contact layer on the sacrificial layer, and removing the sacrificial layer. After the sacrificial layer is removed, the semiconductor layer and the metal contact layer are bonded to each other through a van der Waals bond.

The present invention discloses a neuron and a neuromorphic system including the same. The neuron according to an embodiment of the present invention includes a metal insulator metal (MIM) device including a metal ion-doped insulating layer and configured to perform integration and fire, and the MIM device is formed to have a negative differential resistance (NDR) region in which current decreases as voltage increases.

A method for forming a semiconductor structure comprises: providing a substrate, which includes a first area and a second area arranged in sequence in a second direction, the first area including active layers arranged at intervals in a third direction; forming an initial gate structure located on a surface of each active layer in the first area; etching the initial gate structures to form comb-shaped gate structures stacked in a third direction, each comb-shaped gate structure including first gate structures arranged at intervals in the first direction; and forming bit line structures extending in the third direction and capacitor structures extending in the second direction in the second area, the bit line structures and the capacitor structures are connecting to the first gate structures.