A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.

An integrated circuit device includes a first interconnect layer, and a conductive first interconnect feature and a conductive second interconnect feature laterally separated by a body of insulating or semiconductor material. In an example, the first and second interconnect features are above the first interconnect layer. The integrated circuit device further includes a non-conductive feature above and on the first interconnect feature, and a conductive third interconnect feature above and on the second interconnect feature. The integrated circuit device also includes a second interconnect layer above the non-conductive feature and third interconnect features. In an example, the second and third interconnect features conductively couple the first and second interconnect layers.

A surface recovery process that restores the hydrophobicity of dielectric surfaces and promotes selective deposition of metal-fill such as molybdenum onto metal-containing surfaces while reducing or preventing growth on the dielectric surfaces. Additionally, the surface recovery process reduces film loss against subsequent wet etching processes such as DHF. The recovery precursor soak is performed with optional UV (concurrent or sequential) to react with silanols on damaged dielectric surface to replenish CH3 and recover hydrophobicity of the dielectric surface. The recovery precursor is a carbon-containing recovery precursor, for example, organohalosilanes, esters, silyl ethers, organoaminosilanes, silyl esters, hydrocarbons, or a combination thereof.

A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-aligned contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.

Implementations described herein relate to various structures, integrated assemblies, and memory devices. In some implementations, an apparatus includes a semiconductive region, an insulative region that is adjacent to the semiconductive region, and a conductive line that extends across the semiconductive region and at least a portion of the insulative region. The apparatus includes a contact structure that conjoins with the conductive line and that electrically couples the conductive line with the semiconductive region. The apparatus includes a footing structure that conjoins with the conductive line and that penetrates into the insulative region to anchor the conductive line with the insulative region.