A semiconductor structure is disclosed. The semiconductor structure includes: a semiconductor substrate having a front surface and a back surface facing opposite to the front surface; a filling material extending from the front surface into the semiconductor substrate without penetrating through the semiconductor substrate, the filling material including an upper portion and a lower portion, the upper portion being in contact with the semiconductor substrate; and an epitaxial layer lined between the lower portion of the filling material and the semiconductor substrate. An associated manufacturing method is also disclosed.

A method for manufacturing a semiconductor device according to an embodiment includes preparing a semiconductor layer including a first main surface and a second main surface and including a first semiconductor region of a first conductivity type, a second semiconductor region of a second conductivity type, a control electrode provided so as to face the second semiconductor region, and a third semiconductor region of the first conductivity type, ion-implanting an impurity of the second conductivity type into the first main surface to form a fourth semiconductor region in which an impurity concentration of the second conductivity type is a first concentration, and ion-implanting an impurity of the first conductivity type into the first main surface in an outer peripheral region of the semiconductor layer to form a fifth semiconductor region in which a net impurity concentration of the second conductivity type is a second concentration lower than the first concentration.

There is provided a diode including an anode electrode provided on a side of a front surface of a semiconductor substrate, an interlayer dielectric film disposed between the semiconductor substrate and the anode electrode, a first anode region of a first conductivity type provided on the front surface of the semiconductor substrate, a second anode region of a second conductivity type, which is different from the first conductivity type, provided on the front surface of the semiconductor substrate, a first contact hole provided in the interlayer dielectric film, causing the anode electrode to be in Schottky contact with the first anode region, and a second contact hole provided in the interlayer dielectric film and different from the first contact hole, causing the anode electrode to be in ohmic contact with the second anode region.

A semiconductor device includes a semiconductor substrate, a base region, an emitter region, a collector region, and an element isolation insulating film. The semiconductor substrate has a main surface. The base region has a first conductivity type and is disposed in a surface layer of the semiconductor substrate that is close to the main surface. The emitter region has a second conductivity type and is disposed in a surface layer of the base region. The collector region has the second conductivity type and is disposed at a portion in the surface layer of the semiconductor substrate apart from the emitter region. The element isolation insulating film is disposed on the main surface, and has a thermal oxide film being in contact with a junction interface between the base region and the emitter region.

A method and apparatus for diffusing a dopant within a semiconductor device is described. The method includes performing a dynamic surface anneal in which a substrate is placed inside of a process volume with a mixture of an inert gas and a small amount of oxygen gas. The surface of the substrate is then exposed to one or more rapid laser pulses. The rapid laser bursts diffuse dopant from a doped layer into the substrate. The doped layer is formed during a previous process operation. The temperature and number of laser pulses control the amount of diffusion of the dopant into the substrate. Other dynamic surface anneal operations may be optionally performed before or after the oxygenated dynamic surface anneal operation.

Devices, transistor structures, systems, and techniques are described herein related to gate all around field effect transistors having nanoribbons selectively removed to allow for thicker gate dielectric materials. In forming an alternating stack of semiconductor and sacrificial layers, a cladding layer is applied to those semiconductor layers to be removed during nanoribbon release. Prior to nanoribbon release, atoms of the cladding layer are diffused into only those semiconductor layers having the cladding. During nanoribbon release etch, the sacrificial layers and those semiconductor layers having diffused atoms therein are removed while the semiconductor layers without cladding remain. By removing nanoribbons, an increased ribbon-to-ribbon spacing is attained for application of thicker gate dielectric materials in gate all around field effect transistors.

According to some embodiments of the present disclosure, methods of forming a semiconductor device on a semiconductor layer having opposing first and second surfaces are disclosed. An n-type doped region including an n-type dopant may be formed at the first surface of the semiconductor layer. A p-type dopant source layer including a p-type dopant may be formed on the n-type doped region. The p-type dopant may be diffused from the p-type dopant source layer through the n-type doped region into the semiconductor layer to form a p-type doped region of the semiconductor layer, and the p-type doped region of the semiconductor layer may be between the n-type doped region and the second surface of the semiconductor layer. After diffusing the p-type dopant, the p-type dopant source layer may be removed.

A process for forming a device can include forming a first semiconductor region having a first conductivity type. The process can include depositing a dielectric layer over the first semiconductor region, the dielectric layer having a first etch rate. The process can include forming a first photoresist layer having a second etch rate that is greater than the first etch rate over the dielectric layer and forming a second photoresist layer over the first photoresist layer. The process can include patterning the second photoresist layer to remove a region of the second photoresist, the first photoresist layer being exposed under the region. The process can include etching to form a beveled structure in the dielectric layer. The process can include removing the first photoresist layer and the second photoresist layer and performing ion implantation of the first semiconductor region with dopant species having a second conductivity type.

A conformal boron doping method for a three-dimensional structure includes the steps of: removing a natural oxide layer on a surface of a silicon-based three-dimensional substrate; forming a buffer layer on the surface of the silicon-based three-dimensional substrate; forming a boron oxide thin film on the alumina buffer layer; covering a passivation layer on a surface of the boron oxide thin film; and driving boron impurities containing boron oxide into the silicon-based three-dimensional substrate through the buffer layer by using laser or rapid annealing, to dope the silicon-based three-dimensional substrate. Selecting suitable boron source precursors and oxidants solves the problems of difficult nucleation and inability to form a film after reaching a certain thickness for boron oxide. By selecting alumina as the passivation layer, it is possible to protect the boron oxide thin film from being damaged, and thus achieve damage-free diffusion doping during laser or rapid annealing processes.

The present disclosure provides a DMOS device with a junction field plate and its manufacturing method. A drain region is located on a surface of a semiconductor substrate. A source region is located in the semiconductor substrate at a bottom of a first trench. A gate electrode is located at the bottom of the first trench. The junction field plate improves an effect on reducing surface resistance. At the same time, a depth of trenches in the DMOS device may be reduced, and thereby a depth-to-width ratio of the device is reduced, improving the feasibility of increasing a voltage resistance level. Both the source region and the drain region in the DMOS device are led out on a same surface. A second doped polycrystalline silicon layer includes a first doped sublayer and a second doped sublayer with different conduction types.