A chip package assembly includes a first high-power chip, a second low-power chip, a thermal cooling device and a heterogeneous thermal interface material (HTIM). The thermal cooling device may overlie the first chip and the second chip. The HTIM includes a first thermal interface material (TIM) and a second TIM. The first TIM overlies the first chip, and the second TIM overlies the second chip. The first TIM includes a material that has a first thermal conductivity and a first modulus of elasticity. The first TIM can reflow when the first die reaches a first TIM reflow temperature. The second TIM comprises at least a polymer material. The second TIM has a second modulus of elasticity that is greater than the first modulus of elasticity and a second thermal conductivity that is less than the first thermal conductivity.

A device package includes a first die directly bonded to a second die at an interface, wherein the interface comprises a conductor-to-conductor bond. The device package further includes an encapsulant surrounding the first die and the second die and a plurality of through vias extending through the encapsulant. The plurality of through vias are disposed adjacent the first die and the second die. The device package further includes a plurality of thermal vias extending through the encapsulant and a redistribution structure electrically connected to the first die, the second die, and the plurality of through vias. The plurality of thermal vias is disposed on a surface of the second die and adjacent the first die.

A display device with high operation stability is provided. The display device comprises a first substrate, a second substrate, and a conductive fluid. The first substrate has a first insulating plate and a switching element. The switching element is formed on the first insulating plate. The second substrate has a second insulating plate, a first electrode, a light-emitting layer, and a second electrode. The second insulating plate faces the first insulating plate. The first electrode is formed on the second insulating plate. The light-emitting layer is formed on the first electrode. The second electrode is formed on the light-emitting layer. The second electrode faces the switching element. The conductive fluid is disposed between the first substrate and the second substrate. The conductive fluid electrically connects the switching element and the second electrode.

A semiconductor package may include a package substrate including first and second surfaces, which are opposite to each other, a first semiconductor chip on the first surface, a first mold layer on the first surface of the package substrate and top and side surfaces of the first semiconductor chip, a second semiconductor chip and a third semiconductor chip stacked on the second surface, a second mold layer on the second surface of the package substrate, bottom and side surfaces of the second semiconductor chip, and bottom and side surfaces of the third semiconductor chip, a vertical conductive pillar provided to penetrate the second mold layer in a vertical direction and horizontally spaced apart from the second and third semiconductor chips, and connection terminals between a bottom surface of the first semiconductor chip and the first surface. The vertical conductive pillar may be placed on the second surface.

A cooling apparatus for a power module is provided. The cooling apparatus includes: a power module including power element chips, and a circuit substrate bonded to the power element chips; a heat sink in contact with the circuit substrate, the heat sink having through-holes formed therein; and a manifold configured to allow cooling fluid to flow therethrough and including a wall portion in contact with the circuit substrate. The wall portion includes at least two or more extended ends that extend in a flow direction of the cooling fluid, and a closed end connected to each of the extended ends. The extended ends partly or completely overlap the power element chips.

Electronic structures and methods of assembly are described in which a lid with pocket sidewalls is mounted on a routing substrate such that the pocket sidewalls laterally surround an electronic component and provide a barrier to outflow of the thermal interface layer outside of the pocket sidewalls, and in particular a thermal interface layer including a liquid metal film.

Implementations of semiconductor packages may include a first substrate coupled to a first die, a second substrate coupled to a second die, and a spacer included within a perimeter of the first substrate and within a perimeter of a second substrate, the spacer coupled between the first die and the second die, the spacer include a junction cooling pipe therethrough.